SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 1181

• Manufacturer Part Number: SAM9G45
• Manufacturer: Atmel Corporation

Specifications of SAM9G45

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

6438G–ATARM–19-Apr-11
Doc. Rev
6438E
Comments
Introduction:
“Two Three-channel 32-bit Timer/Counters” peripheral feature changed into
16-bit Timer/Counters”
ECC row added to
Typos corrected in
RNG --> TRNG (also in
Bus Matrix (MATRIX):
Figure 19-1 “DDR
1 row and 1 column added to
DDR/SDR SDRAM Controller (DDRSDRC):
“NO_OPTI” bit removed.
“DIS_ANTICIP_READ”
Electrical Characteristics:
Section 46.14 “DDRSDRC
Section 46.11 “Touch Screen ADC
Last sentence in the Note added.
SPI Master Mode figure titles reversed between
SPI Master and Slave Mode figure titles edited again, from
Figure 46-8 “SPI Slave Mode 1 and 2”
Table 46-2
Ethernet MAC 10/100 (EMAC):
Wake-on-LAN feature activated, including
“Wake-on-LAN
EMAC interrupt on Wake-on-LAN Event activated.
Peripheral DMA Controller (PDC):
Typos corrected in
Power Management Controller (PMC):
Section 25.12.13 “PMC Programmable Clock
Universal Synchronous Asynchronous Receiver Transmitter (USART):
Section 33. “Universal Synchronous Asynchronous Receiver Transmitter
‘DC Characteristics’, I
Register”.
Table
Table
Figure 6-1 “SAM9G45 Memory Mapping”
Multi-port”, and text above and below added.
.
description edited.
Figure 2-1
8-1: AC97 --> AC97C (also in
23-1: AC97 --> AC97C and TSDAC --> TSADCC
Timings”, list of
Table 19-3
SC
and
(TSADC)”, TTH (ns) formula edited.
values changed.
Table
and
Section 35.4.12 “Wake-on-LAN Support”
Supported speed grade limitations updated.
Table
46-4)
Register”, CSS and SLCMCK fields edited.
Figure 46-5
19-4.
Table 23-1
Figure 46-5 “SPI Master Mode 1 and 2”
and
Figure
and
Table
46-6.
(USART)”, SPI feature added.
41-1), PWMC --> PWM,
“Two Three-channel
and
Section 35.6.26
to
SAM9G45
Change
Request
Ref.
6828
6842
RFO
6797
6871
6776
6800
RFO
6847
6872
6903
6836
6838
RFO
6844
6837
1181