SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 1182

• Manufacturer Part Number: SAM9G45
• Manufacturer: Atmel Corporation

Specifications of SAM9G45

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

1182
Doc. Rev
6438D
SAM9G45
Comments
Introduction:
“Features”
LFBGA replaced by TFBGA in
Section 3. “Signal
VDDCORE removed from “
Supplies”
Section 6.3 “I/O Drive Selection and Delay Control”
Figure 6.3 was removed.
0x00500000 changed into 0x00400000 in
FAST and SLOW changed into High and Low in
AT91SAM9G45 Debug and Test:
Value 0x819B 05A1 changed into 0x819B 05A1 in
Boot strategies:
Section 11.4.3.1 “NAND Flash
Section 11.4.3.4 “TWI EEPROM Boot”
and TWCK0.
DDR/SDR SDRAM Controller (DDRSDRC):
Watermarks removed from
Electrical Characteristics:
A “Core Power Supply POR Characteristics” section has been added at the end of
Electrical
Section 46.8 “PLL Characteristics”
2 values were added to Clock Characteristics
The following sections were added:
Section 46.15 “Peripheral Timings”
5 ripple values added to
Figure 46-5
Maximum Operating Voltage values edited in
Table 46-2 on page 1135
- V
- I
- Isc max value changed into ‘TBD’.
Table 46-17 on page
Section 46.10, I/O Drive Level, removed.
External Memories:
Section 20.1.6.1 “2x8-bit DDR2”
Section 20.2.8.2 “16-bit LPDDR on EBI”
O
T-
ranges edited.
and V
Characteristics”.
T+
part was edited.
and
edited; V
Figure 46-6
Description”,
1144, and Note below, edited.
HYS
Table 46-2 on page
added.
updated:
Ground pins GND are common to...” sentence in
Section 22. “DDR/SDR SDRAM Controller
titles reversed.
“Features”
Boot”, and
Table 3-1
title changed (was ‘16-bit DDR2’)
, a Startup Time (T) line was added to
Section 46.13 “SMC
and
added
,
part and
Table
Section 6.2.3 “Internal
Table
Touch Screen Analog-to-Digital Converter9
1135.
Table 46-1 on page
Table 46-4
Section 6.3.1 “I/O Drive Selection”
11-3, CS0 changed into CS3.
11-3, TWI, TWD and TWCK changed into TWI0, TWD0
Section 10.6.4 “Debug Unit”
Section 4.1
was added.
Timings”,
and
Table
ROM”.
1135.
Section 46.14 “DDRSDRC
46-5.
(DDRSDRC)”.
Table 46-14
Section 46. “SAM9G45
Section 5.1 “Power
and
part, was edited.
Table
Timings”,
46-16.
6438G–ATARM–19-Apr-11
6769
Change
Request
Ref.
6715
RFO
6647
RFO
6702
6715
6715
6682
RFO
6664
6672
6637
6689
RFO
6741