tm1300 NXP Semiconductors, tm1300 Datasheet - Page 100

• Manufacturer Part Number: tm1300
• Description: Tm-1300 Media Processor
• Manufacturer: NXP Semiconductors

TM1300 Data Book
capture, the byte order with which the 16-bit data is writ-
ten to memory is governed by the LITTLE ENDIAN bit.
The VI LITTLE ENDIAN bit should be set the same as the
DSPCPU endianness (PCSW.BSX). This ensures that
the DSPCPU sees correct 16-bit data.
Figure 6-15
MMIO registers.
associated with raw-mode capture. The initial state is
reached on software or hardware reset as described in
Section 6.1.4, “Hardware and Software
set, all status and control bits are set to ‘0’. In particular,
CAPTURE_ENABLE is set to ‘0’ and no capture takes
place.
Once the software has programmed BASE1 and BASE2
(with the start addresses of two SDRAM buffer areas
and SIZE (in number of samples), it is safe to enable cap-
ture by setting CAPTURE_ENABLE. Note that SIZE is in
samples and must be a multiple of 64, hence setting a
minimum buffer size of 64 bytes for raw8 mode and 128
bytes for raw10 modes. At this point, buffer1 is the active
capture buffer. Data is captured in buffer1 until capture is
disabled or until SIZE samples have been captured. After
every sample, a running address pointer is incremented
by the sample size (one or two bytes). If SIZE samples
have been captured, capture continues (without missing
a sample) in buffer2. At the same time, BUF1FULL is as-
serted. This causes an interrupt on the DSPCPU, if en-
abled by BUF1FULL INTERRUPT ENABLE.
6-10
Figure 6-15. Raw and message passing modes view of VI MMIO registers.
1.
MMIO_BASE
0x10 141C
0x10 1400
0x10 1404
0x10 1408
0x10 1414
0x10 1418
SDRAM buffers must start on a 64-byte boundary.
offset:
illustrates the ‘raw-mode’ view of the VI
Figure 6-16
VI_STATUS (r)
VI_CTL (r/w)
VI_CLOCK (r/w)
VI_BASE1 (r/w)
VI_BASE2 (r/w)
VI_SIZE (r/w)
PRODUCT SPECIFICATION
shows the major VI states
Highway bandwidth error ACK
31
Reset”. Upon re-
software RESET
SELFCLOCK
DIAGMODE
Little endian
RESERVED
27
Highway bandwidth error
1
)
SLEEPLESS
23
Capture enable
INT enable
Buffer2 is now the active capture buffer and behaves as
described above. In normal operation, the DSPCPU will
respond to the BUF1FULL event by assigning a new
BASE1 and (optionally) SIZE and performing an ACK1.
If the DSPCPU fails to assign a new buffer1 and per-
forms an ACK1 before buffer2 also fills up, the OVER-
RUN condition is raised and capture stops. Capture con-
tinues upon receipt of an ACK1, ACK2, or both,
regardless of the OVERRUN state. The buffer in which
capture resumes is as indicated in
OVERRUN condition is ‘sticky’ and can only be cleared
by software, by writing a ‘1’ to the ACK_OVR bit in the
VI_CTL register.
If insufficient bandwidth is allocated from the internal
data highway, the VI internal buffers may overflow. This
leads to assertion of the HIGHWAY BANDWIDTH ER-
ROR condition. One or more data samples are lost. Cap-
ture resumes at the correct memory address as soon as
the internal buffer is written to memory. The HBE error
condition is sticky. It remains asserted until it is cleared
by writing a ‘1’ to HIGHWAY BANDWIDTH ERROR
ACK. Refer to
Note that VI hardware uses copies of the BASE and
SIZE registers once capture has started. Modifications of
BASE or SIZE, therefore, have no effect until the start of
the next use of the corresponding buffer.
Note also that the VI_BASE1 and VI_BASE2 addresses
must be 64-byte aligned (the six LSBs are always ‘0’).
SIZE (in samples)
Highway bandwidth error
BASE1
BASE2
19
OVERRUN
BUF2FULL
Interrupt enables
Section 6.7, “Highway Latency and HBE.”
15
DIVIDER
(message mode only)
11
MODE
Philips Semiconductors
OVR
BUF2FULL
BUF1ACTIVE
BUF1FULL
OVERFLOW
OVF
BUF1FULL
ACK_OVR
7
ACK_OVF
Figure
0
0
0
0
0
0
ACK2
0
0
0
3
ACK1
6-16. The
0
0
0
0
0
0
0
0
0
0