tm1300 NXP Semiconductors, tm1300 Datasheet - Page 338

• Manufacturer Part Number: tm1300
• Description: Tm-1300 Media Processor
• Manufacturer: NXP Semiconductors

TM1300 Data Book
flesflags
SYNTAX
FUNCTION
DESCRIPTION
arguments exchanged (
be used in assembly source files.)
r src1 <r src2 and stores a bit vector representing the exception flags into r dest . The argument values are in IEEE
single-precision floating-point format; the result is an integer bit vector. The bit vector stored in r dest has the same
format as the IEEE exception bits in the PCSW. The exception flags in PCSW are left unchanged by this operation. If
an argument is denormalized, zero is substituted before computing the comparison, and the IFZ bit in the result is set.
modification of the destination register. If the LSB of r guard is 1, r dest is written; otherwise, r dest is not changed.
EXAMPLES
A-52
r30 = 0x40400000 (3.0), r40 = 0 (0.0)
r30 = 0x40400000 (3.0)
r10 = 0, r60 = 0x3f800000 (1.0),
r30 = 0x40400000 (3.0)
r20 = 1, r60 = 0x3f800000 (1.0),
r30 = 0x40400000 (3.0)
r30 = 0x40400000 (3.0),
r60 = 0x3f800000 (1.0)
r30 = 0x40400000 (3.0),
r61 = 0xffffffff (QNaN)
r50 = 0x7f800000 (+INF)
r55 = 0xff800000 (-INF)
r60 = 0x3f800000 (1.0),
r65 = 0x00400000 (5.877471754e-39)
r50 = 0x7f800000 (+INF)
The
The
The
[ IF r guard ] flesflags r src1 r src2
if r guard then
r dest
flesflags
flesflags
flesflags
31
0
ieee_flags((float)r src1 < (float)r src2 )
Initial Values
operation optionally takes a guard, specified in r guard . If a guard is present, its LSB controls the
operation is a pseudo operation transformed by the scheduler into an
operation computes the IEEE exceptions that would result from computing the comparison
flesflags
PRODUCT SPECIFICATION
’s r src1 is
flesflags r30 r40
flesflags r30 r30
IF r10 flesflags r60 r30
IF r20 flesflags r60 r30
flesflags r30 r60
flesflags r30 r61
flesflags r50 r55
flesflags r60 r65
flesflags r50 r50
IEEE status flags from floating-point compare
fgtrflags
r dest
Operation
’s r src2 and vice versa). (Note: pseudo operations cannot
7
0
OFZ
r80
r90
r120
r121
r125
r126
r127
6
IFZ
5
r100
r110
INV
4
Function unit
Operation code
Number of operands
Modifier
Modifier range
Latency
Issue slots
r80
r90
no change, since guard is false
r110
r120
r121
r125
r126
r127
OVF
3
fles iles fleqflags
Philips Semiconductors
pseudo-op for fgtrflags
0
0
UNF
0
0
0x10 (INV)
0
0x20 (IFZ)
0
ATTRIBUTES
2
SEE ALSO
readpcsw
fgtrflags
Result
INX
1
less-than
DBZ
0
fcomp
with the
145
No
—
2
1
3