tm1300 NXP Semiconductors, tm1300 Datasheet - Page 166

• Manufacturer Part Number: tm1300
• Description: Tm-1300 Media Processor
• Manufacturer: NXP Semiconductors

TM1300 Data Book
• writing to SDRAM_BASE moves the origin of any
• writing to MMIO_BASE moves devices around, and
• writing to both registers in sequence requires a delay,
Figure 11-8. PCI interface registers accessible in MMIO address space.
11-10
executing DSPCPU program, which will cause it to
fail
moves MMIO_BASE and SDRAM_BASE around
due to the implementation. It is recommended to
space such writes far apart, or iterate until the first
register written to reads back with the new value
before writing the second one.
MMIO_base
0x10 300C
0x10 301C
0x10 302C
0x10 3004
0x10 3008
0x10 3010
0x10 3014
0x10 3018
0x10 3020
0x10 3024
0x10 3028
0x10 3030
0x10 3034
0x10 3038
0x10 0000
0x10 0400
offset:
BIU_STATUS (r/w)
BIU_CTL (r/w)
PCI_ADR (r/w)
PCI_DATA (r/w)
CONFIG_ADR (r/w)
CONFIG_DATA (r/w)
CONFIG_CTL (r/w)
IO_ADR (r/w)
IO_DATA (r/w)
IO_CTL (r/w)
SRC_ADR (r/w)
DEST_ADR (r/w)
DMA_CTL (r/w)
INT_CTL (r/w)
DRAM_BASE (r/w)
MMIO_BASE (r/w)
PRODUCT SPECIFICATION
31
31
31
31
31
31
27
27
27
27
27
27
T
D
RMA Received Master Abort
RTA Received Target Abort
23
23
23
23
23
23
RMD (Read Multiple Disable)
Error: Duplicate io_cycle or config_cycle
TTE Target Timer Expired
11.7.4
The BIU_Status register holds bits that track the status of
bus cycles initiated by the DSPCPU and bus cycles from
external devices that write into SDRAM.Two bits of sta-
tus are provided for each type of bus cycle: a busy bit and
a done bit. The DSPCPU can read both bits; a done bit
is cleared by writing a ‘1’ to it. The status register also
holds two error-flag bits.
DSPCPU software must check the busy bits to avoid is-
suing a PCI interface bus cycle request while a request
of a similar type is in progress. If a bus cycle is issued
SDRAM Base Address
MMIO Base Address
DN
Error: Duplicate dma_cycle
19
19
19
19
19
19
SR (PCI Set Reset)
Destination Address
Configuration Data
PCI Address
CR (PCI Clear Reset)
Source Address
BIU_STATUS Register
I/O Address
PCI Data
I/O Data
IE (ICP DMA Enable)
PCI-to-SDRAM
HE (Host Enable)
Reserved
15
15
15
15
15
15
dma_cycle
TL
11
RW (Read/Write)
11
RW (Read/Write)
11
11
11
11
Philips Semiconductors
Done
io_cycle
IS
config_cycle
Busy
BO (Burst Mode Off)
SE (Byte Swap Enable)
FN
Done
Busy
7
7
7
7
7
7
Done
IE
Busy
IntE
RN
Done
Busy
3
P
P
3
3
3
3
3
INT
BE
BE
T
T
0
BN
M
M
0
0
0
0
0
0
0