tm1300 NXP Semiconductors, tm1300 Datasheet - Page 48

• Manufacturer Part Number: tm1300
• Description: Tm-1300 Media Processor
• Manufacturer: NXP Semiconductors

TM1300 Data Book
Although the processor core runs a real-time operating
system to coordinate all activities in the TM1300 system,
the core is not intended for true general-purpose comput-
er use. For example, the TM1300 processor core does
not implement demand-paged virtual memory, memory
address translation, or 64-bit floating point - all essential
features in a general-purpose computer system.
TM1300 uses a VLIW architecture to maximize proces-
sor throughput at the lowest possible cost. VLIW archi-
tectures have performance exceeding that of supersca-
lar general-purpose CPUs without the cost and
complexity of a superscalar CPU implementation. The
hardware saved by eliminating superscalar logic reduces
cost and allows the integration of multimedia-specific
features that enhance the power of the processor core.
The TM1300 operation set includes all traditional micro-
processor operations. In addition, multimedia operations
are included that dramatically accelerate standard video
and audio compression and decompression algorithms.
As just one of the five operations issued in a single
TM1300 instruction, a single ‘custom’ or ‘media’ opera-
tion can implement up to 11 traditional microprocessor
operations. These multimedia operations combined with
the VLIW architecture result in tremendous throughput
for multimedia applications.
The DSPCPU core is supported by separate 16-KB data
and 32-KB instruction caches. The data cache is dual-
ported to allow two simultaneous accesses; both caches
are 8-way set-associative with a 64-byte block size.
2.5.3
The Video In (VI) unit interfaces directly to any CCIR
601/656-compliant device that outputs 8-bit parallel,
4:2:2 YUV time-multiplexed data. Such devices include
direct digital camera systems, which can connect glue-
lessly to TM1300 or through the standard CCIR 656 con-
nector with only the addition of ECL level converters. A
single chip external device can be used to convert to/
from serial D1 professional video. Non-CCIR-compliant
devices can use a digital video decoder chip, such as the
Philips SAA7113H, to interface to TM1300.
The VI unit demultiplexes the captured YUV data before
writing it into local TM1300 SDRAM. Separate planar
data structures are maintained for Y, U, and V.
The VI unit can be programmed to perform on-the-fly
horizontal resolution subsampling by a factor of two if
needed. Many camera systems capture a 640-pixel/line
or 720-pixel/line image. With subsampling, direct conver-
sion to a 320-pixel/line or a 360-pixel/line image can be
performed with no DSPCPU intervention. Performing
this function during video input reduces initial storage
and bus bandwidth requirements for applications requir-
ing reduced resolution.
2.5.4
The Enhanced Video Out (EVO) unit essentially per-
forms the inverse function of the VI unit. EVO generates
an 8-bit, CCIR656 digital video data stream that contains
a composited video and graphics overlay image. The vid-
2-4
Video In Unit
Enhanced Video Out Unit
PRODUCT SPECIFICATION
eo image is taken from separate Y, U, and V planar data
structures in SDRAM. The graphics overlay is taken from
a pixel-packed YUV data structure in SDRAM. Compos-
iting allows both alpha-blending and chroma keying.
The EVO unit can also upscale the video image horizon-
tally by a factor of two to convert from CIF/SIF to CCIR
601 resolution. The overlay image, if enabled, is always
in full-pixel resolution.
The EVO unit is capable of pixel emission rates up to 40
Mpix/sec and allows full programming of a horizontal and
vertical frame/field structure. It is thus capable of refresh-
ing both interlaced and non-interlaced (‘two f
plays with 4:3 or 16:9 or other aspect ratios.
The sample rate for EVO unit pixels is independently and
dynamically programmable. The high-quality, on-chip
sample clock generator circuit allows the programmer
subtle control over the sampling frequency so that audio
and video synchronization can be achieved in any sys-
tem configuration. When changing the sample frequen-
cy, the instantaneous phase does not change, which al-
lows sample frequency manipulation without introducing
audio or video distortion.
2.5.5
The ICP off-loads common image scaling or filtering
tasks from the DSPCPU. Although these tasks can be
easily performed by the DSPCPU, they are a poor use of
the relatively expensive CPU resource. When performed
in parallel by the ICP, these tasks are performed effi-
ciently by simple hardware, which allows the DSPCPU to
continue with more complex tasks.
The ICP can operate as either a memory-to-memory or
a memory-to-PCI coprocessor device.
In memory-to-memory mode, the ICP can perform either
horizontal or vertical image filtering and resizing. A high
quality algorithm is used (5-tap polyphase filter in each
direction). Filtering or scaling is done in either the hori-
zontal or vertical direction in one pass. Two invocations
of the ICP are required to filter or resize in both direc-
tions.
In memory-to-PCI mode, the ICP can perform horizontal
resizing followed by color-space conversion. For exam-
ple, assume an n
window on the PC video screen while the PC is running
a graphical user interface. The first step (if necessary)
would use the ICP in memory-to-memory mode to per-
form a vertical resizing. The second step would use the
ICP in memory-to-PCI mode to perform horizontal resiz-
ing and optional colorspace conversion from YUV to
RGB.
While sending the final, resampled and converted pixels
over the PCI bus to the video frame buffer, the ICP uses
a full, per-pixel occlusion bit mask—accessed in destina-
tion coordinates—to determine which pixels are actually
written to the graphics card frame buffer for display. Con-
ditioning the transfer with the bit mask allows TM1300 to
accommodate an arbitrary arrangement of overlapping
windows on the PC video screen.
Image Coprocessor
m pixel array is to be displayed in a
Philips Semiconductors
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