tm1300 NXP Semiconductors, tm1300 Datasheet - Page 96

• Manufacturer Part Number: tm1300
• Description: Tm-1300 Media Processor
• Manufacturer: NXP Semiconductors

TM1300 Data Book
• FIELD2: Indicates whether the field currently being
Table 6-3
and the number of active pixels per line, lines per field,
and fields per second. Note that any source is accept-
able to VI, as long as the maximum VI_CLK rate is not
exceeded.
Table 6-3. Common video source parameters.
Figure 6-9
captured image. The incoming field consists of N hori-
zontal lines, each line having M pixels labeled 0 through
M–1. Lines are numbered from 0 through N–1. The cap-
tured image is a subset of the incoming image. It is de-
fined by the capture parameters (START_X, START_Y,
WIDTH, HEIGHT) held in the VI_CAP_START and
VI_CAP_SIZE MMIO registers (see
• START_X: defines the starting pixel number (X-coor-
• START_Y: defines the starting line number (Y-coordi-
• WIDTH: Defines the width of the captured image in
• HEIGHT: Defines the height of the captured image in
Image capture starts after the following conditions are
met:
• VI_CTL.CAPTURE ENABLE is asserted.
• VI_STATUS.CAPTURE COMPLETE is de-asserted,
• CUR_Y = START_Y occurs.
Once image capture is started, HEIGHT ‘lines’ are cap-
tured. Each line capture starts if:
• The previous line capture, if any, is completed.
• CUR_X = START_X
6-6
CCIR601
50 Hz/625 lines
CCIR601
60 Hz/525 lines
square pixel
50 Hz/625 lines
square pixel
60 Hz/525 lines
Video Source
received is a field1 or 2. This flag gets updated based
on the F field of every received SAV code. Note that
field1 is the ‘top’ field, i.e. the field containing the top-
most visible line. Field1 contains lines 1,3,5 etc.
Field2 contains lines 2,4,6,8 etc.
dinate of the starting pixel). START_X must be even,
and greater than or equal to ‘0’.
nate of the starting pixel). START_Y must be greater
than or equal to ‘0’.
pixels. WIDTH must be even.
lines.
indicating that any previously captured image has
been acknowledged.
illustrates common digital camera standards
shows the details of an incoming field and the
(# active pixels)
720
720
768
640
M
PRODUCT SPECIFICATION
(# active lines)
Figure
288
240
288
240
N
6-11).
Field
Rate
(Hz)
50
60
50
60
Once line capture starts, it continues for 2*WIDTH pixel
clocks
the presence of one or more EAV codes.
Note that capture continues regardless of any horizontal
or vertical retrace and associated CUR_Y or CUR_X re-
set. This provides special applications with the ability to
capture information embedded inside the horizontal or
vertical blanking interval. If it is desirable to capture pix-
els in the horizontal blanking interval, a minimum time
separation of 1 s is required between the last pixel cap-
tured on line y and the first pixel captured on line y+1. An
exception to this rule is allowed if and only if the storage
parameters below are chosen such that the last and first
pixel end up in adjacent memory locations. Note that
blanking information capture only makes sense in fullres
mode with co-sited sampling. All other modes apply filter-
ing, which will distort the numeric sample values.
The captured image is stored in SDRAM at a location de-
fined by the storage parameters in MMIO registers
(Y_BASE_ADR, Y_DELTA, U_BASE_ADR, U_DELTA,
V_BASE_ADR, V_DELTA). Note that the base-address
registers force alignment to 64-byte boundaries (six
LSBs are always zero). The default memory packing is
big-endian although little-endian packing is also support-
ed by setting the LITTLE_ENDIAN bit in the VI_CTL reg-
ister.
• Y_BASE_ADR: The desired starting (byte) address
• Y_DELTA: The desired address difference between
• U_BASE_ADR,
Horizontally-adjacent samples are stored at successive
byte addresses, resulting in a packed form (four 8-bit
samples are packed into one 32-bit word). Upon horizon-
tal retrace, pixel storage addresses are incremented by
the corresponding DELTA to compute the starting byte
address for the next line. Note that DELTA is a 16-bit un-
signed quantity. This process continues until HEIGHT
lines of WIDTH samples have been stored in memory for
luminance (Y). For chrominance, HEIGHT lines of half
the WIDTH are stored
Modifications to Y_BASE_ADR, U_BASE_ADR and
V_BASE_ADR have no effect until the start of next cap-
ture, i.e. VI hardware maintains a separate pointer to
track the current address. Modifications to Y_DELTA,
1.
2.
in SDRAM memory where the first Y (luminance)
sample of the captured image will be stored. This
address is forced to be 64-byte aligned (six LSBs
always ‘0’).
the last sample of a line and the address of the first
sample on the next line. Note that the value of
Y_DELTA must be chosen so that all line-start
addresses are 64-byte aligned.
V_DELTA: Same functions and alignment restrictions
as above, but for chrominance-component samples.
Four clocks for each C
luminance pixels
Note that consecutive pixel components of each line
are stored in consecutive memory addresses but con-
secutive lines need not be in consecutive memory ad-
dresses
1
in which VI_DVALID is asserted, irrespective of
2
. See
U_DELTA,
b
,Y,C
Philips Semiconductors
Figure
r
,Y group representing two
6-10.
V_BASE_ADR,