tm1300 NXP Semiconductors, tm1300 Datasheet - Page 133

• Manufacturer Part Number: tm1300
• Description: Tm-1300 Media Processor
• Manufacturer: NXP Semiconductors

Philips Semiconductors
(AI SER_MASTER=0, AI_SCK and AI_WS externally
wired to the corresponding AO pins). In such systems, in-
dependent software control over A/D and D/A sampling
rate is not possible, but component count is minimized.
Table 8-3.AI MMIO clock & interface control bits
8.5
The AI unit can accept data in a wide variety of serial
data framing conventions.
tion
CLOCK_EDGE=0, a frame is defined with respect to the
positive transition of the AI_WS signal, as observed by a
positive clock transition on AI_SCK. Each data bit sam-
pled on positive AI_SCK transitions has a specific bit po-
sition: the data bit sampled on the clock edge after the
clock edge on which the AI_WS transition is seen has bit
position 0. Each subsequent clock edge defines a new
bit position. As defined in
of POLARITY and CLOCK_EDGE can be used to define
a variety of serial frame bitposition definitions.
The capturing of samples is governed by FRAMEMODE.
If FRAMEMODE=00, every serial frame results in one
sample from the serial-parallel converter. A sample is de-
fined as a left/right pair in stereo modes or a single left
channel value in mono modes. If FRAMEMODE=1y, the
serial frame data bit in bit position VALIDPOS is exam-
ined. If it has value ‘y’, a sample is taken from the data
stream (the valid bit is allowed to precede or follow the
left or right channel data provided it is in the same serial
frame as the data).
The left and right sample data can be in a LSB-first or
MSB-first form, at an arbitrary bit position, and with an ar-
bitrary length.
Figure 8-2. AI serial frame and bit position definition (POLARITY=1, CLOCK_EDGE=0).
SER_MASTER
FREQUENCY
SCKDIV
WSDIV
AI_SCK
AI_WS
Field Name
AI_SD
of
SERIAL DATA FRAMING
a
serial
0
1
0
is the timing master over the serial inter-
face. AI_SCK and AI_WS are set to be
inputs.
1
serial interface. The AI_SCK and AI_WS
pins are set to be outputs.
Sets the clock frequency emitted by the
AI_OSCLK output. RESET default 0.
Sets the divider used to derive AI_SCK
from AI_OSCLK. Set to 0..255, for divi-
sion by 1..256. RESET default 0.
Sets the divider used to derive AI_WS
from AI_SCK. Set to 0..511 for a serial
frame length of 1..512. RESET default 0.
2
frame.
(RESET default), the A/D converter
TM1300 is timing master over the AI
3
4
Table
Figure 8-2
5
6
Description
If
8-4, other combinations
7
POLARITY=1
8
illustrates the no-
9
10
11
12
13
14
and
15
16
17
frame
18
Table 8-4. AI MMIO serial framing control fields
In MSB-first mode, the serial-to-parallel converter as-
signs the value of the bit at LEFTPOS to LEFT[15]. Sub-
sequent bits are assigned, in order, to decreasing bit po-
sitions in the LEFT data word, up to and including
LEFT[SSPOS]. Bits LEFT[SSPOS–1:0] are cleared.
Hence, in MSB-first mode, an arbitrary number of bits are
captured. They are left-adjusted in the 16-bit parallel out-
put of the converter.
In LSB-first mode, the serial to parallel converter assigns
the value of the bit at LEFTPOS to LEFT[SSPOS]. Sub-
PRODUCT SPECIFICATION
POLARITY
FRAMEMODE
VALIDPOS
LEFTPOS
RIGHTPOS
DATAMODE
SSPOS
CLOCK_EDGE • if ‘0’(RESET default) the AI_SD and AI_WS
19
Field Name
n
20
21
22
23
24
0
(RESET default)
1
00
(RESET default)
01
10
11
• Defines the bit position within a serial frame
• Default 0.
• Defines the bit position within a serial frame
• Default 0.
• Defines the bit position within a serial frame
• Default 0.
0
1
• Start/Stop bit position. Default 0.
• If DATAMODE=MSB first, SSPOS deter-
• If DATAMODE=LSB first, SSPOS deter-
• if 1, AI_SD and AI_WS are sampled on neg-
25
where the valid bit is found.
where the first data bit of the left channel is
found.
where the first data bit of the right channel
is found.
mines the bit index (0..15) in the parallel
word of the last data bit. Bits 15 (MSB) up
to/including SSPOS are taken in order from
the serial frame data. All other bits are set
to ‘0’.
mines the bit index (0..15) in the parallel
word of the first data bit. Bits SSPOS up to/
including 15 are taken in order from the
serial frame data. All other bits are set to ‘0’.
pins are sampled on positive edges of the
AI_SCK pin. If SER_MASTER =1, AI_WS is
asserted on negative edges of AI_SCK.
ative edges of AI_SCK. As output, AI_WS
is asserted on positive edges of AI_SCK.
26
serial frame starts on AI_WS negedge
serial frame starts on AI_WS posedge
MSB first (RESET default)
LSB first
accept a sample every serial frame
unused, reserved
accept sample if valid bit = 0
accept sample if valid bit = 1
27
28
29
30
Description
31
0
1
2
3
frame
Audio In
4
n+1
5
6
8-3
7