tm1300 NXP Semiconductors, tm1300 Datasheet - Page 235

• Manufacturer Part Number: tm1300
• Description: Tm-1300 Media Processor
• Manufacturer: NXP Semiconductors

I
16.1
TM1300 includes an
control many different multimedia devices such as:
• DMSDs - Digital multi-standard decoders
• DENCs - Digital encoders
• Digital cameras
• I
The key features of the
• Supports I
• I
• Support for the 7-bit addressing option of the I
• Provisions for full software use of I
Note that the I
parameters and/or code from a serial EEPROM as de-
scribed in
only active upon TM1300 hardware reset and quiescent
afterwards.
A typical system using the
Figure
series of slave devices through SCL and SDA. Note that
the bus has one pullup resistor for each of the clock and
data lines. The pullup should be set to a voltage no high-
er than VREF_PERIPH.
16.2
The following are the main
• The SEX bit is removed. Endian-ness is fixed.
• The
Figure 16-1. Typical I
2
specification
for implementing software I
C Interface
2
2
C - Parallel I/O expanders
C data rate up to 400 kbits/sec
SCL
SDA
16-1. The TM1300 is connected as a master to a
I
I
NEW IN TM1300
2
2
C
C OVERVIEW
Section 13, “System
clock rate is closer to 100/400 kHz
2
2
C single master mode
C pins are also used to load the initial boot
TM1300
I
2
C
2
Slave
I
C system implementation
I
2
2
interface which can be used to
C
C
I
interface are:
2
I
2
C
Slave
C
I
2
2
differences from TM1000:
C
C or similar protocols
interface is presented in
Boot”. The boot logic is
+ VREF_PERIPH
R
2
p
C interface pins
R
p
2
C
• The GDI bit now correctly indicates write-completion
• Clock stretching is always enabled.
16.3
The
shown in
Table 16-1. I
16.4
The
the programmer. The registers are mapped into the
MMIO address space and are fully accessible to the pro-
grammer.
sure compatibility with future devices, any undefined
MMIO bits should be ignored when read, and written as
‘0’s.
16.4.1
The IIC_AR is the I
master receive and transmit modes. This register is writ-
ten with the address(es) of the
bytecount for transmit/receive.
field definitions for the IIC_AR register.
Table 16-2. IIC_AR Register
ADDRESS must be programmed to contain the 7 bits of
the desired slave address
The DIRECTION bitfield controls read/write operation on
the
• DIRECTION = 0 –> I
PRODUCT SPECIFICATION
IIC_SDA
IIC_SCL
31:25
23:16
Signal
Bits
15:8
7:0
24
I
I
2
I
2
2
C
C
C
by Essam Abu-ghoush, Robert Nichols
interface. The bit definition is:
EXTERNAL INTERFACE
I
user interface consists of four registers visible to
external interface is composed of two signals as
2
Table
C REGISTER SET
IIC_AR Register
Figure 16-2
DIRECTION
Field Name
ADDRESS
reserved
reserved
COUNT
2
Type
C External interface
I/O
O
16-1.
2
C
I
I
address register and is used in both
2
2
C serial data
C
shows the
2
7-bit slave device address.
Read/Write control bit
must be written to ‘0’
Byte count of requested transfer
Read as ‘0’
clock
C write
Chapter 16
I
2
Table 16-2
Description
C
I
2
C
Definition
slave device and the
register set. To en-
lists the bit-
16-1