tm1300 NXP Semiconductors, tm1300 Datasheet - Page 165

• Manufacturer Part Number: tm1300
• Description: Tm-1300 Media Processor
• Manufacturer: NXP Semiconductors

Philips Semiconductors
location of these bits is described in
tailed EEPROM Contents.”
obtained from the PCI SIG. The vendor is free to assign
subsystem ID’s.
11.6.13 Expansion ROM Base Address
The Expansion ROM Base Address register is similar in
purpose to the SDRAM and MMIO Base Address regis-
ters. This register relocates a separate memory aperture
for PCI devices that wish to implement additional ROM.
TM1300 does not implement expansion ROM; conse-
quently, the least-significant bit of this register—which in-
dicates whether or not TM1300 responds to expansion
ROM accesses—is hardwired to ’0’. All other bits also
read as ’0’s.
11.6.14 Interrupt Line Register
The value of the Interrupt Line Register determines
which input of the system interrupt controller is driven by
TM1300’s interrupt pin. As it configures the system and
assigns resources, host system software writes this reg-
ister to assign one of the system interrupt lines to
TM1300.
11.6.15 Interrupt Pin Register
The value of the Interrupt Pin Register determines which
interrupt pin TM1300 uses.
values for this register.
Table 11-11. Interrupt pin encodings
Since TM1300 uses inta#, the value of this register is
hardwired to ‘1’.
11.6.16 Max_Lat, Min_Gnt Registers
The value in the Max_Lat register specifies how often the
TM1300 PCI interface needs access to the PCI bus. The
value in the Min_Gnt register specifies the minimum
length for a burst period on the PCI bus.
Both of these timer values are specified as multiples of
250 ns. Values of ’0’ indicate that a device has no specif-
ic requirements for latency and burst-length.
For TM1300, Max_Lat is hardwired to 0x01 (250 ns), and
Min_Gnt is hardwired to 0x03 (750 ns).
Interrupt Pin
all others
1
2
3
4
Register
Use interrupt pin inta#
Use interrupt pin intb#
Use interrupt pin intc#
Use interrupt pin intd#
Reserved
Table 11-11
A legal Vendor ID must be
Meaning
Section 13.5, “De-
lists the possible
11.7
The TM1300 PCI interface contains 13 MMIO registers;
most, except the status bits in BIU_Status, are usually
written only by the DSPCPU.
ported cycles sequenced by the PCI interface and the
registers involved in each cycle. To ensure compatibility
with future devices, all undefined MMIO bits should be ig-
nored when read, and written as ’0’s.
The MMIO registers are all accessible to DSPCPU soft-
ware, and all but the PCI_ADR and PCI_DATA registers
are accessible to external PCI initiators. The facilities of
TM1300’s PCI interface can be useful to external initia-
tors in certain circumstances. For example:
• The PCI DMA engine might be useful during host-
• Host-resident diagnostics may want to test the PCI
• The MMIO registers can be used to diagnose mal-
Note, however, that external PCI initiators can access
MMIO registers in only one way: as 32-bit words on nat-
urally aligned, 32-bit addresses. If any other type of ac-
cess is attempted, the results are undefined. Also, the
byte order of the external initiator and the PCI interface
must be the same; otherwise, the result of an access with
disagreeing byte order is undefined.
For easy reference,
together with their offsets from MMIO_BASE and their
accessibility by the DSPCPU and external PCI initiators.
Figure 11-8
MMIO registers. The following are detailed descriptions
of the MMIO registers.
11.7.1
The DRAM_BASE register in MMIO space is a shadow
copy of the DRAM_BASE register in PCI Configuration
space. See
for more details. This copy provides MMIO-space access
to this register. The P,T and M bitfields of this MMIO reg-
ister are read-only.
11.7.2
The MMIO_BASE register in MMIO space is a copy of
the MMIO_BASE register in PCI Configuration space.
See
more details. This shadow copy provides MMIO-space
access to this register. The P,T and M bitfields of this
MMIO register are read-only.
11.7.3
The DRAM_BASE and MMIO_BASE registers are not
normally written through MMIO; their value is determined
by the boot process. Though not recommended, the reg-
isters are writable in MMIO. Special care should be exer-
cised when writing these registers:
PRODUCT SPECIFICATION
assisted boot.
interface during boot.
functioning parts.
Section 11.6.11, “Base Address Registers,”
REGISTERS IN MMIO SPACE
DRAM_BASE Register
MMIO_BASE Register
MMIO/DRAM_BASE updates
Section 11.6.11, “Base Address Registers,”
shows the formats of the PCI interface
Table 11-13
Table 11-12
lists the MMIO registers
PCI Interface
lists the sup-
11-9
for