tm1300 NXP Semiconductors, tm1300 Datasheet - Page 134

• Manufacturer Part Number: tm1300
• Description: Tm-1300 Media Processor
• Manufacturer: NXP Semiconductors

TM1300 Data Book
sequent bits are assigned, in order, to increasing bit po-
sitions in the LEFT data word, up to and including
LEFT[15]. Bits LEFT[SSPOS–1:0] are cleared. Hence, in
LSB-first mode, an arbitrary number of bits are captured.
They are returned left-adjusted in the 16-bit parallel out-
put of the converter.
Table 8-5. Example setup for SAA7366
Refer to
how the AI unit MMIO registers are set to collect 16-bit
samples using the Philips SAA7366 I
8-4
AI_SCK
Figure 8-3. Serial frame of the SAA7366 18 bit I
SER_MASTER
FREQUENCY
SCKDIV
WSDIV
POLARITY
FRAMEMODE
VALIDPOS
LEFTPOS
RIGHTPOS
DATAMODE
SSPOS
CLOCK_EDGE
Figure 8-4. AI memory DMA formats.
AI_WS
AI_SD
8-bit
mono
8-bit
stereo
16-bit
mono
16-bit
stereo
Field
Figure 8-3
0
161628209 256f
left
left
1
Value
adr
adr
n/a
and
63
00
32
0
3
0
0
0
0
0
n
n
2
left
3
n
Table 8-5
left
left
(18)
adr
adr
PRODUCT SPECIFICATION
n
n
SAA7366 is serial master
AI_SCK set to AI_OSCLK/4
(not needed since
SER_MASTER=0)
Serial frame length of 64 bits
(not needed since
SER_MASTER=0)
Frame starts with neg. AI_WS
Take a sample each ser. frame
Don’t care
Bit position 0 is MSB of left
channel and will go to
LEFT[15]
Bit position 32 is MSB of right
channel and will go to
RIGHT[15]
MSB first
Stop with LEFT/RIGHT[0]
Sample WS and SD on posi-
tive SCK edges for I
left
adr+1
adr+1
right
s
n+1
44.1 kHz
n
to see an example of
Explanation
2
S 18-bit A/D con-
18
19
left
left
adr+2
adr+2
2
n+2
n+1
S
31
left
adr+2
adr+2
right
2
32
S A/D converter (format 2 SWS).
n+1
n
33
right
left
adr+3
adr+3
34
right
n+3
n+1
n
(18)
verter. This setup assumes the SAA7366 acts as the se-
rial master.
For example, if it were desirable to use only the 12 MSBs
of the A/D converter in
Table 8-5
LEFT[15:4] being set with data bits 0..11, and LEFT[3:0]
being set to ’0’. RIGHT[15:4] is set with data bits 32..43
and RIGHT[3:0] is set to ’0’.
8.6
The AI unit autonomously writes samples to memory in
mono and stereo 8- and 16-bits per sample formats, as
shown in
stored at increasing memory address locations. The set-
ting of the LITTLE_ENDIAN bit in the AI_CTL register de-
termines how increasing memory addresses map to byte
positions within words. Refer to
for details on byte ordering conventions.
The AI hardware implements a double buffering scheme
to ensure that no samples are lost, even if the DSPCPU
is highly loaded and slow to respond to interrupts. The
DSPCPU software assigns buffers by writing a base ad-
dress and size to the MMIO control fields described in
Table
software synchronization.
In 8-bit capture modes, the eight MSBs of the serial par-
allel converter output data are written to memory. In 16-
bit capture modes, all bits of the parallel data are written
to memory. If SIGN_CONVERT is set to ’1’, the MSB of
the data is inverted, which is equivalent to translating
from two’s complement to offset binary representation.
This allows the use of an external two’s complement 16-
bit A/D converter to generate 8-bit unsigned samples,
which is often used in PC audio.
8-6. Refer to
adr+4
left
adr+4
left
MEMORY DATA FORMATS
n+4
n+2
Figure
with SSPOS set to ‘4’. This results in
50
adr+4
left
adr+4
left
51
n+2
n+1
8-4. Successive samples are always
52
right
Section 8.7
adr+5
left
adr+5
n+5
n+2
Figure
62
Philips Semiconductors
63
0
8-3, use the settings of
for details on hardware/
Appendix C, “Endian-ness,”
left
left
adr+6
adr+6
1
n+6
n+3
left
right
n+1
left
adr+6
adr+6
(18)
n+3
n+1
right
left
adr+7
adr+7
n+7
n+3