tm1300 NXP Semiconductors, tm1300 Datasheet - Page 97

• Manufacturer Part Number: tm1300
• Description: Tm-1300 Media Processor
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Figure 6-10. VI YUV 4:2:2 planar memory format.
U_DELTA and V_DELTA do affect the next horizontal re-
trace. Hence, under normal circumstances, the DELTA
variables should not be changed during capture.
When capture is complete, i.e. any internal VI buffers
have been flushed and the entire captured image is in lo-
cal SDRAM, VI raises the STATUS register flag CAP-
TURE COMPLETE. If enabled in the VI_CTL register,
this event causes a DSPCPU interrupt to be requested.
The programmer can determine whether the captured
image is a field1 or field2 by inspection of the FIELD2
flag in VI_STATUS. Note that the FIELD2 flag changes
at the start of the vertical blanking interval of the next
field.
The CAPTURE COMPLETE flag is cleared by writing a
word to VI_CTL with a ‘1’ in the CAPTURE COMPLETE
ACK bit position. This action has the following effect:
• it tells the hardware that a new Y,U, and V DMA
• it clears the CAPTURE COMPLETE flag
• it tells VI to capture the next image
The user can program the Y_THRESHOLD field to gen-
erate pre-completion (or post-completion) interrupts.
Whenever CUR_Y reaches Y_THRESHOLD, the
THRESHOLD REACHED flag in the STATUS register is
set. If enabled in the VI_CTL register, this event causes
a DSPCPU interrupt request. The THRESHOLD
REACHED flag is cleared by writing a word to VI_CTL
with a ‘1’ in the THRESHOLD REACHED ACK bit posi-
tion. Note that, due to internal buffering in the VI unit, it is
NOT guaranteed that all samples from lines up to and in-
cluding CUR_Y have been written to local SDRAM upon
THRESHOLD REACHED. The implementation guaran-
tees a fixed maximum time of 2 s between raising the
interrupt and completion of all writes to SDRAM. The
buffer is available (or the old one has been copied)
U_BASE_ADR
Y_BASE_ADR
U_DELTA
Y_DELTA
pix0
pix0
WIDTH/2 pixels
pix1
pix2
pix2
•
•
WIDTH pixels
•
THRESHOLD interrupt mechanism works regardless of
CAPTURE ENABLE. Hence, it can also be used to skip
a desired number of fields without constant DSPCPU
polling of VI_STATUS.
If VI internal buffers overflow due to insufficient internal
data-highway bandwidth allocation, the HIGHWAY
BANDWIDTH ERROR condition is raised in the
VI_STATUS register. If enabled, this causes assertion of
a VI interrupt request. Capture continues at the correct
memory address as soon as the internal buffers can be
written to memory, but one or more pixels may have
been lost, and the corresponding memory locations are
not written. The HBE condition can be cleared by writing
a ‘1’ to the HIGHWAY BANDWIDTH ERROR ACK bit in
VI_CTL. Refer to
HBE”
Any interrupt event of VI (CAPTURE COMPLETE,
THRESHOLD REACHED, HIGHWAY BANDWIDTH ER-
ROR) leads to the assertion of a single VI interrupt
(SOURCE 9) to the TM1300 Vectored Interrupt Control-
ler. The interrupt handler routine should check the STA-
TUS register to determine the set of VI events associated
with the request. The vectored interrupt controller should
always be set to have VI (SOURCE 9) operate in level
sensitive mode. This ensures that each event is handled.
VI asserts the interrupt request line as long as one or
more enabled events are asserted. The interrupt handler
clears one or more selected events by writing a ‘1’ to the
corresponding ACK field in VI_CTL. The clearing of the
last event leads to immediate (next DSPCPU clock edge)
de-assertion of the interrupt request line to the Vectored
Interrupt Controller. See
(Maskable and Non-Maskable Interrupts),”
tion on how to program interrupt handler routines.
PRODUCT SPECIFICATION
•
•
for more information.
•
(Repeated for V_BASE_ADDR,
W–1
pix
V_DELTA)
Section 6.7, “Highway Latency and
Section 3.5.3, “INT and NMI
for informa-
Video In
6-7