tm1300 NXP Semiconductors, tm1300 Datasheet - Page 177

• Manufacturer Part Number: tm1300
• Description: Tm-1300 Media Processor
• Manufacturer: NXP Semiconductors

Philips Semiconductors
12.6
Memory system parameters are determined by the con-
tents of two configuration registers, MM_CONFIG and
PLL_RATIOS.
these registers, and
ensure compatibility with future devices, any undefined
MMIO bits should be ignored when read.
MM_CONFIG and PLL_RATIOS are loaded from the
boot EEPROM, as described in
EEPROM Contents.”
ory interface is held in reset state. After the memory in-
terface is released from reset, the contents of these reg-
isters cannot be altered.
These registers are visible in MMIO space. They can be
read, but writes have no effect.
12.6.1
The MM_CONFIG register tells the memory interface
how to use the local DRAM memory. The fields in this
register tell the interface the rank size and the refresh
rate of the memory.
functions.
REFRESH (Refresh interval). The 16-bit REFRESH
field specifies the number of memory-system clock cy-
cles between refresh operations. The default value of
Figure 12-2. Memory interface configuration registers.
Figure 12-3. TM1300 memory and core PLL connections.
MMIO_base
0x10 0100
0x10 0300
offset:
MEMORY SYSTEM PROGRAMMING
Memory System Clocks
External Clock Input
MM_CONFIG Register
TRI_CLKIN
MM_CLK1
MM_CLK0
MM_CONFIG (r/o)
PLL_RATIOS (r/o)
Table 12-4
Figure 12-2
During this boot process, the mem-
Table 12-6
describes the function of
shows their formats. To
Section 13.5, “Detailed
summarizes the field
Memory System
31
31
SD SB CD CB SR
7
6
PLL
5
4
3
2
CR
0
PLL_RATIOS Register
this register is 1000 (0x03E8). See
fresh,”
Bit 3 of MM_CONFIG must be set to ‘0’ for normal oper-
ation.
SIZE (Rank size). The 3-bit SIZE field specifies the size
of each rank of DRAM. Each rank must be the size spec-
ified by SIZE. The default is a rank size of 4MB. Refer to
Table 12-5
12.6.2
The PLL_RATIOS register controls the operation of the
separate memory-interface and CPU PLLs. Fields in this
register determine if the PLLs are active and what in-
put:output ratio each PLL should generate.
summarizes the field functions.
the PLLs are connected and how fields in the
PLL_RATIOS register control them.
CR (CPU-to-memory PLL ratio). The 3-bit CR field se-
lects one of five input-to-output clock ratios for the CPU
PLL. The input clock is the memory system clock; the
output clock determines the TM1300 core operating fre-
quency. The default value is ‘0’, which implies a 1:1
CPU:memory ratio. See
SR (Memory-to-external PLL ratio). The 1-bit SR field
selects one of two memory-to-external clock ratios for
the memory interface PLL. The PLL input is TM1300’s
PRODUCT SPECIFICATION
19
for more information.
DSPCPU PLL
PLL_RATIOS Register
for the interpretation of this field.
SDRAM PLL Bypass
SDRAM PLL Disable
REFRESH
CPU PLL Bypass
CPU PLL Disable
Table 12-6
SDRAM Memory System
SDRAM Ratio
Figure 12-3
SB SD CB CD SR
7
TM1300
for other encodings.
Section 12.11, “Re-
CPU Ratio
6
5
TM1300
Core
Clock
4
4
3
0
3
shows how
Table 12-6
2
2
SIZE
CR
12-3
0
0