tm1300 NXP Semiconductors, tm1300 Datasheet - Page 39

• Manufacturer Part Number: tm1300
• Description: Tm-1300 Media Processor
• Manufacturer: NXP Semiconductors

Philips Semiconductors
1.9.4.7
Notes: 1. For best high speed SDRAM operation, 50-ohm matched PCB traces are recommended for all MM_xxx signals.
1.9.4.8
The following specifications meet the PCI Specifications, Rev. 2.1 for 33-MHz bus operation.
Notes: 1. See the timing measurement conditions in
f
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
SDRAM
on-PCI
rst-PCI
rst-clk-PCI
rst-off-PCI
CS
PD
OH
SU
IH
val-PCI (Bus)
val-PCI (ptp)
Off-PCI
su-PCI
su-PCI (ptp)
h-PCI
Symbol
Symbol
a. PCI Clock skew between two PCI devices must be lower than 1.8ns instead of 2ns as specified in PCI 2.1.
2. Equal load circuit. MM_CLK0 and MM_CLK1 are matched output buffers.
3. The center of the two rising edges on MM_CLK0, MM_CLK1 are used as the clock reference point.
4. MM_CLK0 is used as a reference clock.
2. Minimum times are measured at the package pin with the load circuit shown in
3. REG# and GNT# are point-to-point signals and have different input setup times. All other signals are bused.
4. See the timing measurement conditions in
5. RST# is asserted and de-asserted asynchronously with respect to CLK.
6. All output drivers are floated when RST# is active.
7. For the purpose of Active/Float timing measurements, the Hi-Z or ‘off’ state is defined to be when the total current delivered
Use 27-33 ohm series terminator resistors close to TM1300 in the MM_CLK0 and MM_CLK1 line only.
Propagation delay guarantee is defined from 50% point of clock edge to 50% level on D/A/C.
Output hold time guarantee is defined from 50% point of clock edge to 50% level on D/A/C.
Input setup time requirement is defined as data value 50% complete to 50% level on clock.
Input hold time requirement is defined as minimum time from 50% level on clock to 50% change on data.
with the load circuit shown in
through the component pin is less than or equal to the leakage current specification.
SDRAM interface timing
PCI Bus timing
MM_CLK frequency
Skew between MM_CLK0, CLK1
Propagation delay of data, address, control
Output hold time of data, address and control
Input data setup time
Input data hold time
Clk to signal valid delay, bused signals
Clk to signal valid delay, point-to-point signals
Float to active delay
Active to float delay
Input setup time to CLK - bused signals
Input setup time to CLK - point-to-point signals
Input hold time from CLK
Reset active time after power stable
Reset active time after CLK stable
Reset active to output float delay
Figure 1-6
Parameter
Parameter
and
Figure
Figure
Figure
1-4.
1-5.
1-7.
PRODUCT SPECIFICATION
Min.
TM1300-143
1.5
1.0
1.5
Min.
0.2
100
12
2
2
2
7
1
a
Max
143
0.1
5.0
Max
Figure
11
12
28
40
TM1300-166/180
Min.
1.5
0.4
1.5
1-8. Maximum times are measured
Units
ms
ns
ns
ns
ns
ns
ns
ns
ns
s
Max
143
4.5
0.1
Notes
1,2,3
1,2,3
5,6,7
1,7
3,4
3,4
Units
MHz
1
4
5
5
ns
ns
ns
ns
ns
Pin List
Notes
1
2
3
3
4
4
1-15