tm1300 NXP Semiconductors, tm1300 Datasheet - Page 447

• Manufacturer Part Number: tm1300
• Description: Tm-1300 Media Processor
• Manufacturer: NXP Semiconductors

Philips Semiconductors
16-bit store
pseudo-op for h_st16d(0)
SYNTAX
FUNCTION
DESCRIPTION
arguments. (Note: pseudo operations cannot be used in assembly files.)
address in r src1 . This store operation is performed as little-endian or big-endian depending on the current setting of
the bytesex bit in the PCSW.
MSE (Misaligned Store Exception) bit in the PCSW register is set to 1. Additionally, if the TRPMSE (TRaP on
Misaligned Store Exception) bit in PCSW is 1, exception processing will be requested on the next interruptible jump.
defined only for 32-bit loads and stores.
modification of the addressed memory locations (and the modification of cache if the locations are cacheable). If the
LSB of r guard is 1, the store takes effect. If the LSB of r guard is 0, st16 has no side effects whatever; in particular, the
LRU and other status bits in the data cache are not affected.
EXAMPLES
r10 = 0xd00, r80 = 0x44332211
r50 = 0, r20 = 0xd01,
r70 = 0xaabbccdd
r60 = 1, r30 = 0xd02,
r70 = 0xaabbccdd
The
The
If
The result of an access by
The
[ IF r guard ] st16 r src1 r src2
if r guard then {
}
st16
if PCSW.bytesex = LITTLE_ENDIAN then
else
mem[r src1 + (1
mem[r src1 + (0
st16
st16
st16
bs
bs
is misaligned (the memory address in r src1 is not a multiple of 2), the result of
1
0
Initial Values
operation stores the least-significant 16-bit halfword of r src2 into the memory locations pointed to by the
operation is a pseudo operation transformed by the scheduler into an
operation optionally takes a guard, specified in r guard . If a guard is present, its LSB controls the
bs)]
bs)]
r src2 <7:0>
r src2 <15:8>
st16
st16 r10 r80
IF r50 st16 r20 r70
IF r60 st16 r30 r70
to the MMIO address aperture is undefined; access to the MMIO aperture is
Operation
PRODUCT SPECIFICATION
[0xd00]
no change, since guard is false
[0xd02]
DSPCPU Operations for TM1300
Function unit
Operation code
Number of operands
Modifier
Modifier range
Latency
Issue slots
st16d h_st16d st8 st8d
h_st16d(0)
0x22, [0xd01]
0xcc, [0xd03]
st16
ATTRIBUTES
st32 st32d
SEE ALSO
Result
is undefined, and the
0xdd
0x11
with the same
st16
dmem
4, 5
n/a
No
30
—
2
A-161