tm1300 NXP Semiconductors, tm1300 Datasheet - Page 135

• Manufacturer Part Number: tm1300
• Description: Tm-1300 Media Processor
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Table 8-6. AI MMIO DMA control fields
Figure 8-5. AI status/control field MMIO layout.
LITTLE_ENDIAN
BASE1
BASE2
SIZE
CAP_MODE
SIGN_CONVERT
Field Name
MMIO_base
0x10 1C0C
0x10 1C1C
0x10 1C00
0x10 1C04
0x10 1C08
0x10 1C10
0x10 1C14
0x10 1C18
offset:
0
(RESET default)
1
Base address of buffer1; a 64-byte aligned
address in local SDRAM.
RESET default 0.
Base address of buffer2; a 64-byte aligned
address in local SDRAM.
RESET default 0.
• Number of samples to be placed in
• Stereo modes: a pair of 8- or 16-bit data
• Mono modes: a single value is 1 sample
• RESET default 0.
00
(RESET default).
01
10
11
0
default)
1
buffer before switching to other buffer
is 1 sample
AI_STATUS (r/w)
AI_CTL (r/w)
AI_SERIAL (r/w)
AI_FRAMING (r/w)
AI_FREQ (r/w)
AI_BASE1 (r/w)
AI_BASE2 (r/w)
AI_SIZE (r/w)
capture in big endian memory format
capture little endian
leave MSB unchanged (RESET
invert MSB
mono (left ADC only), 16 bits/sample
mono (left ADC only), 8 bits/sample.
stereo, 2 times 8 bits/sample
stereo, 2 times 16 bits/sample
SER_MASTER
CAP_ENABLE
POLARITY
DATAMODE
Description
RESET
FRAMEMODE
SIGN_CONVERT
CAP_MODE
CLOCK_EDGE
LITTLE_ENDIAN
31
31
31
31
31
DIAGMODE
SLEEPLESS
VALIDPOS
27
27
27
27
27
23
23
23
23
23
Note that the AI hardware does not generate A-law or -
law 8-bit data formats. If such formats are desired, the
DSPCPU can be used to convert from 16-bit linear data
to A-law or -law data.
8.7
Figure
tion of the control and status fields of the AI unit. To en-
sure compatibility with future devices, undefined bits in
MMIO registers should be ignored when read, and writ-
ten as ’0’s.
The AI unit is reset by a TM1300 hardware reset, or by
writing 0x80000000 to the AI_CTL register. Upon RE-
SET, capture is disabled (CAP_ENABLE = 0), and
buffer1 is the active buffer (BUF1_ACTIVE=1). A mini-
mum of 5 valid AI_SCK clock cycles is required to allow
internal AI circuitry to stabilize before enabling capture.
This can be accomplished by programming AI_FREQ
and AI_SERIAL and then delaying for the appropriate
time interval.
Programing of the AI_SERIAL MMIO register needs to
follow the following sequence order:
PRODUCT SPECIFICATION
BASE1
BASE2
19
19
19
19
8-5,
19
LEFTPOS
AUDIO IN OPERATION
SIZE (in samples)
FREQUENCY
Table 8-9
15
15
15
15
15
RESERVED
HBE (Highway bandwidth error)
WSDIV
OVR_INTEN
and
HBE_INTEN
11
BUF2_INTEN
11
11
11
11
Table 8-8
BUF1_ACTIVE
BUF1_INTEN
RIGHTPOS
OVERRUN
ACK_OVR
ACK_HBE
7
7
7
7
7
BUF2_FULL
describe the func-
BUF1_FULL
0
0
0
SCKDIV
ACK2
0
0
0
ACK1
Audio In
0
0
0
3
3
3
3
3
SSPOS
0
0
0
0
0
0
8-5
0
0
0
0
0
0
0
0