tm1300 NXP Semiconductors, tm1300 Datasheet - Page 93

• Manufacturer Part Number: tm1300
• Description: Tm-1300 Media Processor
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Figure 6-2. VI unit connected to an EVO unit of another TM1300.
Figure 6-3. VI unit connected to a video decoder.
Figure 6-4. VI connected to a 10-bit video A/D converter.
6.2
The VI block can operate in two distinct clocking modes,
as controlled by the VI_CLOCK control register (see
Figure
SELFCLOCK = 0: ‘External clocking mode’. This is
the most common mode of operation. In this mode, the
VI_CLK pin is an asynchronous clock input. All other in-
puts are sampled on positive edges of the VI_CLK clock
signal. On-chip synchronizers ensure reliable asynchro-
nous capture. This mode can be combined with DIAG-
MODE, in which case the EVO clock acts as the asyn-
chronous clock source. In external clocking mode, the
value of DIVIDER is ignored.
Analog video
6-11).
CLOCK GENERATOR
1–2 S-VHS Y/C
1–4 CVBS
Analog video
(ENDMSG) VO_IO2
(STMSG) VO_IO1
TM1300 1
VO_DATA[7:0]
VO_CLK
SAA7111
10-bit Video A/D
24.576 MHz
VPO[15:8]
SDA
SCL
LLC
To other I
I
2
C bus
SELFCLOCK = 1: ‘Internal clocking mode”. This
mode is typically intended for use with external A/D con-
verters or other sources that require a clock. In this
mode, VI_CLK is an output pin. Positive edges of
VI_CLK are used to sample all other inputs. The gener-
ated clock frequency can be programmed using the DI-
VIDER field in the VI_CLOCK register.
On RESET, VI_CLOCK is set to zero, i.e. external clock-
ing mode is the default with DIVIDER ignored.
PRODUCT SPECIFICATION
2
C devices
logic ‘1’
logic ‘1’
logic ‘1’
GND
VI_DATA[7:0]
VI_DATA[8]
VI_DATA[9]
VI_CLK
VI_DVALID
VI_DATA[9:8]
VI_DATA[7:0]
VI_DVALID
VI_CLK
IIC_SCL
IIC_SDA
VI_DATA[9:0]
VI_DVALID
VI_CLK
f
TM1300 2
VICLK
TM1300
TM1300
=
f
----------------------- -
DIVIDER
DSPCPU
Video In
6-3