tm1300 NXP Semiconductors, tm1300 Datasheet - Page 323
tm1300
Manufacturer Part Number
tm1300
Description
Tm-1300 Media Processor
Manufacturer
NXP Semiconductors
Datasheet
1.TM1300.pdf
(533 pages)
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Philips Semiconductors
Floating-point absolute value
SYNTAX
FUNCTION
DESCRIPTION
values are in IEEE single-precision floating-point format. If an argument is denormalized, zero is substituted for the
argument before computing the absolute value, and the IFZ flag in the PCSW is set. If
exception, the corresponding exception flags in the PCSW are set. The PCSW exception flags are sticky: the flags can
be set as a side-effect of any floating-point operation but can only be reset by an explicit
update of the PCSW exception flags occurs at the same time as r dest is written. If any other floating-point compute
operations update the PCSW at the same time, the net result in each exception flag is the logical OR of all
simultaneous updates ORed with the existing PCSW value for that exception flag.
modification of the destination register. If the LSB of r guard is 1, r dest and the exception flags in PCSW are written;
otherwise, r dest is not changed and the operation does not affect the exception flags in PCSW.
EXAMPLES
r30 = 0x40400000 (3.0)
r35 = 0xbf800000 (-1.0)
r40 = 0x00400000 (5.877471754e-39)
r45 = 0xffffffff (QNaN)
r50 = 0xffbfffff (SNaN)
r10 = 0,
r55 = 0xff7fffff (–3.402823466e+38)
r20 = 1,
r55 = 0xff7fffff (–3.402823466e+38)
The
The
The
[ IF r guard ] fabsval r src1
if r guard then {
}
if (float)r src1 < 0 then
else
fabsvalflags
fabsval
fabsval
r dest
r dest
Initial Values
–(float)r src1
(float)r src1
operation computes the absolute value of the argument r src1 and stores the result into r dest . All
operation optionally takes a guard, specified in r guard . If a guard is present, its LSB controls the
operation computes the exception flags that would result from an individual
fabsval r30
fabsval r35
fabsval r40
fabsval r45
fabsval r50
IF r10 fabsval r55
IF r20 fabsval r55
r dest
Operation
r90
r95
r100
r105
r110
PRODUCT SPECIFICATION
r115
r120
DSPCPU Operations for TM1300
Function unit
Operation code
Number of operands
Modifier
Modifier range
Latency
Issue slots
r90
r95
r100
r105
r110
no change, since guard is false
r120
iabs dspiabs dspidualabs
fabsvalflags readpcsw
writepcsw
0x40400000 (3.0)
0x3f800000 (1.0)
fabsval
0x0 (+0.0), IFZ set
0xffffffff (QNaN)
0xffffffff (QNaN), INV set
0x7f7fffff (3.402823466e+38)
ATTRIBUTES
writepcsw
SEE ALSO
Result
causes an IEEE
fabsval
fabsval
operation. The
falu
115
1, 4
No
—
1
3
.
A-37
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