tm1300 NXP Semiconductors, tm1300 Datasheet - Page 460

• Manufacturer Part Number: tm1300
• Description: Tm-1300 Media Processor
• Manufacturer: NXP Semiconductors

TM1300 Data Book
ufixieee
SYNTAX
FUNCTION
DESCRIPTION
writes the result into r dest . Rounding is according to the IEEE rounding mode bits in PCSW. If r src1 is denormalized,
zero is substituted before conversion, and the IFZ flag in the PCSW is set. If
such as overflow or underflow, the corresponding exception flags in the PCSW are set. The PCSW exception flags are
sticky: the flags can be set as a side-effect of any floating-point operation but can only be reset by an explicit
writepcsw
other floating-point compute operations update the PCSW at the same time, the net result in each exception flag is the
logical OR of all simultaneous updates ORed with the existing PCSW value for that exception flag.
modification of the destination register. If the LSB of r guard is 1, r dest and the exception flags in PCSW are written;
otherwise, r dest is not changed and the operation does not affect the exception flags in PCSW.
EXAMPLES
A-174
r30 = 0x40400000 (3.0)
r35 = 0x40247ae1 (2.57)
r10 = 0,
r40 = 0xff4fffff (–3.402823466e+38)
r20 = 1,
r40 = 0xff4fffff (–3.402823466e+38)
r45 = 0x7f800000 (+INF))
r50 = 0xbfc147ae (-1.51)
r60 = 0x00400000 (5.877471754e-39)
r70 = 0xffffffff (QNaN)
r80 = 0xffbfffff (SNaN)
The
The
The
[ IF r guard ] ufixieee r src1
if r guard then {
}
r dest
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ufixieeeflags
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Initial Values
(unsigned long) ((float)r src1 )
operation. The update of the PCSW exception flags occurs at the same time as r dest is written. If any
operation converts the single-precision IEEE floating-point value in r src1 to an unsigned integer and
operation optionally takes a guard, specified in r guard . If a guard is present, its LSB controls the
PRODUCT SPECIFICATION
operation computes the exception flags that would result from an individual
ufixieee r30
ufixieee r35
IF r10 ufixieee r40
IF r20 ufixieee r40
ufixieee r45
ufixieee r50
ufixieee r60
ufixieee r70
ufixieee r80
Convert floating-point to unsigned integer using
r dest
Operation
r100
r102
r112
r115
r117
r120
r122
r105
r110
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PCSW rounding mode
Function unit
Operation code
Number of operands
Modifier
Modifier range
Latency
Issue slots
r100
r102
no change, since guard is false
r110
r112
r115
r117
r120
r122
ifixieee ifixrz ufixrz
Philips Semiconductors
3
3, INX flag set
0x0, INV flag set
0xffffffff (2
0, INV flag set
0, IFZ set
0, INV flag set
0, INV flag set
causes an IEEE exception,
ATTRIBUTES
SEE ALSO
Result
32
-1), INV flag set
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falu
123
1, 4
No
—
1
3
.