tm1300 NXP Semiconductors, tm1300 Datasheet - Page 128

• Manufacturer Part Number: tm1300
• Description: Tm-1300 Media Processor
• Manufacturer: NXP Semiconductors

TM1300 Data Book
2. In the same modes but with overlay enabled, the la-
• During the first 64 EVO clock cycles at least one
• During 128 EVO clock cycles, the EVO unit must
3. When the EVO is set to image mode with 2 upscal-
At hardware reset, the output multiplexer is set to 0x3,
and the PLL system is disabled. To start the PLL system,
the following steps must be performed:
7-24
Figure 7-32. PLL filter block diagram.
9
During 128 EVO clock cycles, the EVO block must
have 2 requests acknowledged, that is, ([2Ys, 1U and
1V] / 2). For example, if the EVO clock is 27 MHz,
then the EVO must get two requests (128 bytes) from
SDRAM in 128 / 027 = 4740 ns.
The byte bandwidth B
tive image for this case is:
where ceil( X ) is a function returning the least integral
value greater than or equal to X , and W is the
IMAGE_WIDTH field value.
tency is as follows:
request must be acknowledged for the OL data.
have 4 requests acknowledged ([4 OLs, 2 Ys, 1 V
and 1 U] / 2).
For example, if the EVO clock runs at 54 MHz then the
EVO must get the first request from SDRAM in
64/.054 = 1185 ns and must average a bandwidth la-
tency of 4 requests in 128 / .054 = 2370 ns.
Byte bandwidth B
image is then as follows:
B
ing, the latency requirements are multiplied by a factor
of 2. For example, if 1 mode called for one request
per 64 EVO clock cycles, the latency becomes one re-
quest per 128 EVO clock cycles. Bandwidth is roughly
divided by 2:
B
CPU Clock
1 xOL
3
1 x
Square-Wave DDS
=
FREQUENCY
=
ceil
B
1 x
( )
----- -
64
W
+
1x,OL
ceil
+
ceil
0
1x
( )
per video line within the active
----- -
32
W
PRODUCT SPECIFICATION
(
per video line within the ac-
-------- -
128
W
+
) 2
4
div S+1
PLL_S
64
+
4
64
Detect
Phase
4. Latency for data-streaming mode or message-pass-
7.17.5
The EVO block enters in power down state whenever
TM1300 is put in global power down mode, except if the
SLEEPLESS bit in VO_CTL is set. In the latter case, the
block continues DMA operation and will wake up the
DSPCPU whenever an interrupt is generated.
The EVO block can be separately powered down by set-
ting a bit in the BLOCK_POWER_DOWN register. Refer
to
It is recommended that EVO be stopped (by negating
VO_CTL.ENABLE) before block level power down is
started, or that SLEEPLESS mode is used when global
power down is activated.
7.18
The PLL filter reduces the phase jitter of the DDS synthe-
sizer output. It can also be used to multiply the DDS out-
put frequency by 2 . The DDS and PLL filter together
provide a high-quality, accurately-programmable output
video clock. The PLL filter block is shown in
div T+1
1. Assign a DDS frequency. This starts the DDS. Allow
Loop
Filter
PLL_T
Chapter 21, “Power Management.”
B
B
ing mode is as follows:
During 64 EVO clock cycles, the EVO unit must get
one request from SDRAM. For example, if the EVO
clock runs at 38 MHz, then the latency is 64 / .038 =
1684 ns and bandwidth is 38 MB/s.
for at least 31 DSPCPU cycles for the DDS frequency
setting to take effect.
2 x
2 xOL
=
DDS AND PLL FILTER DETAILS
Power Down and Sleepless
=
ceil
8–90 MHz
B
2 x
VCO
(
-------- -
128
W
+
)
ceil
+
ceil
( )
----- -
64
W
CLOCK_SELECT
Philips Semiconductors
(
00
01
10
11
-------- -
256
CLKOUT
W
+
4
) 2
64
+
(to Frame Timing Gen.)
4
Figure
VO_CLK Internal
64
VO_CLK
7-32.