tm1300 NXP Semiconductors, tm1300 Datasheet - Page 237

• Manufacturer Part Number: tm1300
• Description: Tm-1300 Media Processor
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Table 16-3. IIC_SR register
of the IIC_SR register are presented in
IIC_SR provides four sources of interrupts. Note: the in-
terrupt should be set up as level triggered interrupt.
• GDI interrupt — The GDI bit together with the FI bits
• FI interrupt — See GDI bit definition and GDI/FI
• SANACKI interrupt — This interrupt flag bit indicates
• SDNACKI interrupt — This interrupt flag bit indicates
25:23
15:8
Bits
7:0
31
30
29
28
27
26
22
21
provide status about I
interpretation of GDI/FI bit combinations are different
depending on whether the I
transmit or master receive mode. Refer to
and
transmit and receive definitions in
Table
that a slave address was transmitted but no slave on
the I
transaction. This is an error condition. Once the I
interface has set this interrupt flag, the interface is
idle. The DSPCPU should clear this interrupt flag by
writing a ‘1’ to IIC_CR.CLRSANACKI before re-
attempting this transfer or starting another I
fer.
that an addressed slave receiver device has refused
to acknowledge the current byte of data for an ongo-
ing transfer. This is an error condition. Once the I
interface has set this interrupt flag, the interface is
Table 16-6
2
DIRECTION Direction of current data transfer.
C bus acknowledges the address to claim the
Field Name
16-6.
SDA_STAT
SCL_STAT
SANACKI
SDNACKI
Reserved
Reserved
STATE
RBC
GDI
FI
for GDI/FI interpretation.
Good Data Interrupt. This is the nor-
mal transfer complete interrupt flag.
This interrupt may be asserted without
the IIC_SR.FI interrupt bit at the end of
an I
an I
Full Interrupt. This interrupt indicates
the condition of the IIC_DR register
dependent upon whether the I
face is in receive or transmit mode.
Slave Address No Acknowledge Inter-
rupt.
Slave Data No Acknowledge Interrupt.
This bit is used to examine the state of
the external I
polarity is:
1 = SDA pad is low
0 = SDA pad floated high
This bit is used to examine the state of
the external I
polarity is:
1 = SCL pad is low
0 = SCL pad floated high
The STATE field indicates the microac-
tivity of the I
Read as ‘0’
Remaining Byte Count.
Read as ‘0’
2
2
C transfer or after master abort of
C transfer.
2
C transfer completion. The
2
2
C interface is in master
2
2
C bus.
Definition
C SDA data pin. Bit
C SCL clock pin. Bit
Table
Table 16-4
Table 16-4
16-3. The
2
2
C trans-
C inter-
and
2
2
C
C
Table 16-4. Master transmit mode GDI/FI status
Table 16-5. STATE field values
Table 16-6. Master receive GDI/FI conditions
The SDA_STAT and SCL_STAT bits indicate the current
state of the SDA and SCL signals. The STATE field indi-
cates the microactivity of the I
ues and their meanings are presented in
DIRECTION status bit indicates if the
transmit or receive mode.
• if DIRECTION = 0 then I
• if DIRECTION = 1 then I
The RBC bitfield indicates the remaining bytecount for an
I
as a read-only ‘shadow register’ for the IIC_AR.COUNT
bitfield. During
the remaining bytecount. To avoid corrupting an
PRODUCT SPECIFICATION
2
GDI
GDI
C
0
0
1
0
0
1
idle. The DSPCPU should clear this interrupt flag by
writing a ‘1’ to IIC_CR.CLRSDNACKI before retrying
this transfer or starting another.
STATE
transfer in progress. The IIC_SR.RBC bitfield serves
000
001
010
011
100
101
110
111
FI
X
0
1
FI
X
0
1
Meaning
I
RESERVED FOR FUTURE USE
IDLE (MSG is done, awaiting clear GDI to go to
000 state)
Address phase is being processed
BYTE3 (first byte) is being processed
BYTE2 is being processed
BYTE1 is being processed
BYTE0 (last) is being processed
Message is not complete. The IIC_DR is not
empty. No interrupt.
Message is not complete. The IIC_DR is empty
and the requested transmit byte count is not
equal to 0. The DSPCPU must write additional
bytes of the current transfer to the IIC_DR regis-
ter.
Message transmission has completed. The
IIC_DR is empty. The byte transmit count = 0.
2
Message is not complete. IIC_DR is not full.
No interrupt.
IIC_DR contains received data and needs to
be read serviced. More data bytes are
expected since the receive byte count is not
equal to 0.
The transfer has been completed and the
receive byte count is equal to 0. 0 to 4 valid
bytes are in the IIC_DR register awaiting read
servicing by the DSPCPU.
C Interface is idle.
I
2
C
transfer, the RBC bitfield will reflect
2
2
C is a transmitter.
C is a receiver.
Description
Description
2
C interface. The field val-
I
2
C
I2C Interface
Table 16-5
interface is in
16-3
The
I
2
C