tm1300 NXP Semiconductors, tm1300 Datasheet - Page 102

• Manufacturer Part Number: tm1300
• Description: Tm-1300 Media Processor
• Manufacturer: NXP Semiconductors

TM1300 Data Book
6.7
Refer to
biter terminology used here. The VI unit uses internal
buffering before writing data to SDRAM. There are two
internal buffers, each 16 entries of 32 bits.
In fullres mode, each internal buffer is used for 128 Y
samples, 64 U samples, and 64 V samples. Once the
first internal buffer is filled, 4 highway transactions must
occur before the second buffer fills completely. Hence,
the requirement for not losing samples is:
• 4 requests must be served within 256 VI clock cycles.
For the typical CCIR601-resolution NTSC or PAL 27-
MHz VI clock rate, the latency requirement is 4 requests
in 9481 ns (25600/27). This can be used as one request
every 2370 ns or, with a TM1300 SDRAM clock speed of
100 MHz, every 237 SDRAM clock cycles. The one re-
quest latency is used to define the priority raising value
(see
In halfres mode, the Y, U, and V decimation by 2 takes
place before writing to the internal buffers. So, the re-
quirement for not loosing samples is:
• 4 requests served within 512 VI clock cycles.
For halfres subsampling, NTSC or PAL 27-MHz VI clock
rate and TM1300 SDRAM clock speed of 100 MHz, la-
tency is 4 requests in 51200/27 = 18962 ns (1896 high-
way clock cycles) or one request every 4740 ns (474
SDRAM clock cycles).
6-12
Figure 6-18. VI message passing mode major states.
Section 20.6.3 on page
HIGHWAY LATENCY AND HBE
Chapter 20, “Arbiter,”
ACK2
RESET
No EOM
No EOM
PRODUCT SPECIFICATION
(
(
See text in
See text in
20-8).
for a description of the ar-
raise OVERFLOW*
raise OVERFLOW*
Section
Section
6.6)
6.6)
ACTIVE = BUF1
ACTIVE = BUF2
ACTIVE = BUF2
ACTIVE = BUF1
BUF1FULL
BUF2FULL
ACK1
EOM
EOM
For raw8 capture and message passing modes, each in-
ternal buffer stores 64 samples at the incoming VI clock
rate. The latency requirement is one request served ev-
ery 64 VI clock cycles.
For the raw10 capture modes, each internal buffer stores
32 samples. Hence, the requirement for not losing sam-
ples is one request served every 32 VI clock cycles.
For a 38-MHz data rate on the incoming 10-bit samples
and a TM1300 SDRAM clock speed of 100 MHz, high-
way latency should be set to guarantee less than 3200/
38 = 842 ns (84 SDRAM clock cycles) per clock cycle.
This cannot be met if any other peripherals are enabled.
Table 6-4
latency (in SDRAM clock cycles) needed to guarantee
that no samples are lost. The general formula uses ‘F’ to
represent the VI clock frequency (in MHz).
Table 6-4. VI highway latency requirements (27-MHz
data rate, 100-MHz TM1300 highway clock)
fullres capture
halfres capture
raw8
raw10s
raw10u
message passing
* OVERRUN and OVERFLOW are sticky flags. They are set,
but do not affect operation. They can only be cleared by soft-
ware, by writing a ‘1’ to ACK_OVR or ACK_OVF.
(See text in
Mode
summarizes the maximum allowed highway
Section
raise OVERRUN*
BUF1FULL
BUF2FULL
Max latency setting
(27 MHz, 100 MHz)
6.6)
Philips Semiconductors
237
474
237
118
118
237
Formula
12,800/F
6,400/F
6,400/F
3,200/F
3,200/F
6,400/F