tm1300 NXP Semiconductors, tm1300 Datasheet - Page 347

• Manufacturer Part Number: tm1300
• Description: Tm-1300 Media Processor
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Floating-point subtract
SYNTAX
FUNCTION
DESCRIPTION
single-precision floating-point format. Rounding is according to the IEEE rounding mode bits in PCSW. If an argument
is denormalized, zero is substituted for the argument before computing the difference, and the IFZ flag in the PCSW is
set. If the result is denormalized, the result is set to zero instead, and the OFZ flag in the PCSW is set. If
an IEEE exception, the corresponding exception flags in the PCSW are set. The PCSW exception flags are sticky: the
flags can be set as a side-effect of any floating-point operation but can only be reset by an explicit
operation. The update of the PCSW exception flags occurs at the same time as r dest is written. If any other floating-
point compute operations update the PCSW at the same time, the net result in each exception flag is the logical OR of
all simultaneous updates ORed with the existing PCSW value for that exception flag.
modification of the destination register. If the LSB of r guard is 1, r dest and the exception flags in PCSW are written;
otherwise, r dest is not changed and the operation does not affect the exception flags in PCSW.
EXAMPLES
r60 = 0xc0400000 (–3.0),
r30 = 0x3f800000 (1.0)
r40 = 0x40400000 (3.0),
r60 = 0xc0400000 (–3.0)
r10 = 0, r40 = 0x40400000 (3.0),
r80 = 0x00800000 (1.17549435e-38)
r20 = 1, r40 = 0x40400000 (3.0),
r80 = 0x00800000 (1.17549435e-38)
r40 = 0x40400000 (3.0),
r81 = 0x00400000 (5.877471754e–39)
r82 = 0x00c00000 (1.763241526e-38),
r83 = 0x0080000 (1.175494351e-38)
r84 = 0x7f800000 (+INF),
r85 = 0x7f800000 (+INF)
r70 = 0x7f7fffff (3.402823466e+38)
r86 = 0xff7fffff (-3.402823466e+38)
r87 = 0xffffffff (QNaN))
r30 = 0x3f800000 (1.0
r87 = 0xffbfffff (SNaN))
r30 = 0x3f800000 (1.0
r83 = 0x0080001 (1.175494421e-38),
r89 = 0x0080000 (1.175494351e-38)
The
The
The
[ IF r guard ] fsub r src1 r src2
if r guard then
fsubflags
fsub
fsub
r dest
Initial Values
operation computes the difference r src1 –r src2 and writes the result into r dest . All values are in IEEE
operation optionally takes a guard, specified in r guard . If a guard is present, its LSB controls the
(float)r src1 – (float)r src2
operation computes the exception flags that would result from an individual
fsub r60 r30
fsub r40 r60
IF r10 fsub r40 r80
IF r20 fsub r40 r80
fsub r40 r81
fsub r82 r83
fsub r84 r85
fsub r70 r86
fsub r87 r30
fsub r87 r30
fsub r83 r89
r dest
Operation
r90
r95
r111
r112
r113
r120
r125
r125
r126
PRODUCT SPECIFICATION
r100
r110
DSPCPU Operations for TM1300
r90
r95
no change, since guard is false
r110
r111
r112
r113
r120
set
r125
r125
r126
Function unit
Operation code
Number of operands
Modifier
Modifier range
Latency
Issue slots
fsubflags isub dspisub
dspidualsub readpcsw
0xc0800000 (-4.0)
0x40c00000 (6.0)
0x7f800000 (+INF), OVF, INX flag
0x40400000 (3.0), INX flag set
0x40400000 (3.0), IFZ flag set
0x0, OFZ flag set
0xffffffff (QNaN), INV flag set
0xffffffff (QNaN)
0xffffffff (QNaN), INV flag set
0x0, UNF flag set
ATTRIBUTES
writepcsw
SEE ALSO
Result
fsub
.
fsub
writepcsw
fsub
falu
113
1, 4
No
—
causes
2
3
A-61