tm1300 NXP Semiconductors, tm1300 Datasheet - Page 112

• Manufacturer Part Number: tm1300
• Description: Tm-1300 Media Processor
• Manufacturer: NXP Semiconductors

TM1300 Data Book
Figure 7-15. EVO VO_IO1 timing in FIELD_SYNC mode.
7.10
In Genlock mode, the EVO is not synchronization master
but receives frame timing signals on VO_IO2. The EVO
operates in Genlock mode when SYNC_MASTER = 0,
EVO_CTL.EVO_ENABLE = 1 and EVO_CTL.GEN-
LOCK = 1.
The active edge can be programmed using the
VO_CTL.VO_IO2_POS bit. The initial transition of the
frame timing signal on VO_IO2 causes the Frame Line
Counter
VO_FRAME.FRAME_PRESET.
FRAME_LENGTH, the Frame Line Counter starts count-
ing again from 1.
EVO_SLVDLY.SLAVE_DLY is typically used to compen-
sate for any delay in the frame timing source or internal
pipeline synchronization anywhere in a line. Internally,
the active edge of VO_IO2 is delayed by SLAVE_DLY
VO_CLK clock cycles. Typically, it will allow FRAME_
PRESET to be loaded at the beginning of a new line.
With
FRAME_PRESET loaded, the TM1300 can generate
frames totally synchronized with the active edge of
VO_IO2. All the internal MMIO registers (except of
course VO_CTL) should be programmed with the same
values as for SYNC_MASTER mode. See
In Genlock mode, the EVO is free-running according to
the values programmed in its internal registers before the
initial VO_IO2 active edge. Just after receiving the active
edge that will synchronize the EVO, output values may
7-8
Figure 7-14. EVO VO_IO2 timing in FIELD_SYNC mode.
Vertical
Sync
VO_IO2
NTSC
PAL
Video
Lines
GENLOCK MODE
correct
to
1
4
be
Image Data
Blanking
values
VO_IO1
set
PRODUCT SPECIFICATION
22
19 20
EAV
Blanking
of
to
23
Active Video
Field 1
SAV
One Line
SLAVE_DLY
After
the
Figure
Field Width, Pixels
value
Image Line: Image Width
263 264
310 311
reaching
Image Width, Pixels
7-16.
and
Blanking
in
One Frame
312 313
265 266
be erroneous for several VO_CLK cycles, but it is guar-
anteed that the next frame will be correct.
After the first synchronizing edge, if the next one hap-
pens according to the values programmed in the EVO
MMIO registers, no change will appear in the output tim-
ing of the EVO. If the active edge of VO_OI2 does not
match the programmed value, a new synchronization
phase is performed.
Typically, this is programmed as follows: SLAVE_DLY is
loaded with the number of clock cycles for one video line
minus the number of delay cycles used by the EVO to
synchronize itself. FRAME_PRESET is programmed
with the value 2. With this programming, the active edge
of VO_IO2 will happen just before the first byte (pream-
ble) of the first line.
The first active edge of VO_IO2 is delayed internally by
SLAVE_DLY VO_CLK cycles so that it appears internally
just before the start of the second line minus the internal
EVO pipeline delay. After this internal pipeline delay, the
line counter is loaded by FRAME_PRESET, (‘2’), and the
EVO starts sending data for line 2.
For the next frame, if the internal EVO programming
matches the VO_IO2 timing, the EVO will appear to start
the first byte of the first line just after the VO_IO2 active
signal.
7.11
In data-streaming and message-passing modes, the
EVO supplies a stream of 8-bit data. No data selection or
Blanking
DATA TRANSFER TIMING
Blanking
EAV
335 336
282
Field 2
283
Active Video
Philips Semiconductors
525
623 624 625 1
Blanking
1
3
4