tm1300 NXP Semiconductors, tm1300 Datasheet - Page 51

• Manufacturer Part Number: tm1300
• Description: Tm-1300 Media Processor
• Manufacturer: NXP Semiconductors

DSPCPU Architecture
3.1
This section documents the system programmer or
‘bare-machine’ view of the TM1300 CPU (or DSPCPU).
3.1.1
Default reset value of PCSW register is 0x800. This new
reset value allows Audio Out and SPDIF Out timestamp
registers to be in phase with CCCOUNT (lower 32 bits).
3.1.2
Figure 3-1
registers, r0...r127. In addition to the hardware program
counter, PC, there are 4 user-accessible special purpose
registers, PCSW, DPC (destination program counter),
SPC (source program counter), and CCCOUNT.
Table 3-1
Register r0 always contains the integer value '0', corre-
sponding to the boolean value 'FALSE' or the single-pre-
cision floating point value +0.0. Register r1 always con-
tains the integer value '1' ('TRUE'). The programmer is
NOT allowed to write to r0 or r1.
Figure 3-1. TM1300 registers.
Note: Writing to r0 or r1 may cause reads from r0 or
r1 scheduled in adjacent clock cycles to return unpre-
dictable values. The standard assembler prevents/for-
bids the use of r0 or r1 as a destination register.
63
128 General-Purpose Registers
System Status & Control Registers
BASIC ARCHITECTURE CONCEPTS
• r0 & r1 fixed
• r2–r127 variable
New in TM1300
Register Model
lists the registers and their purposes.
shows the DSPCPU’s 128 general purpose
55
47
39
31
31
0
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Registers r2 through r127 are true general purpose reg-
isters; the hardware does not imply their use in any way,
though compiler or programmer conventions may assign
particular roles to particular registers. The DPC and SPC
relate to interrupt and exception handling and are treated
in
tion Program Counter.”
and Status Word) register is treated in
“PCSW Overview.”
counter is treated in
Cycle Counter.”
Table 3-1. DSPCPU registers
PRODUCT SPECIFICATION
CCCOUNT 64 bits Counts clock cycles since reset
Register
Section 3.1.5, “SPC and DPC—Source and Destina-
r2–r127
PCSW
DPC
SPC
PC
23
23
r0
r1
by Gert Slavenburg, Marcel Janssens
32 bits Always reads as 0x0; must not be used
32 bits Always reads as 0x1; must not be used
32 bits 126 general-purpose registers
32 bits Program counter
32 bits Program control & status word
32 bits Destination program counter; latches
32 bits Source program counter; latches target
Size
15
15
•
•
•
as destination of operations
as destination of operations
target of taken branch that is interrupted
of taken branch that is not interrupted
CCCOUNT, the 64-bit clock cycle
Section 3.1.6, “CCCOUNT—Clock
The PCSW (Program Control
7
7
Chapter 3
Details
0
0
0
0
1
0
Section 3.1.4,
r0
r1
r2
r3
r126
r127
PC
PCSW
DPC
SPC
CCCOUNT
•
•
•
3-1