tm1300 NXP Semiconductors, tm1300 Datasheet - Page 449

• Manufacturer Part Number: tm1300
• Description: Tm-1300 Media Processor
• Manufacturer: NXP Semiconductors

Philips Semiconductors
32-bit store
pseudo-op for h_st32d(0)
SYNTAX
FUNCTION
DESCRIPTION
arguments. (Note: pseudo operations cannot be used in assembly files.)
value is an opcode modifier and must be a multiple of 4. This store operation is performed as little-endian or big-
endian depending on the current setting of the bytesex bit in the PCSW.
MSE (Misaligned Store Exception) bit in the PCSW register is set to 1. Additionally, if the TRPMSE (TRaP on
Misaligned Store Exception) bit in PCSW is 1, exception processing will be requested on the next interruptible jump.
memory operations is undefined). The state of the BSX bit in the PCSW has no effect on MMIO access by
modification of the addressed memory locations (and the modification of cache if the locations are cacheable). If the
LSB of r guard is 1, the store takes effect. If the LSB of r guard is 0, st32 has no side effects whatever; in particular, the
LRU and other status bits in the data cache are not affected.
EXAMPLES
r10 = 0xd00, r80 = 0x44332211
r50 = 0, r20 = 0xd01,
r70 = 0xaabbccdd
r60 = 1, r30 = 0xd04,
r70 = 0xaabbccdd
The
The
If
The
The
[ IF r guard ] st32 r src1 r src2
if r guard then {
}
st32
if PCSW.bytesex = LITTLE_ENDIAN then
else
mem[r src1 + (3
mem[r src1 + (2
mem[r src1 + (1
mem[r src1 + (0
st32
st32
st32
st32
bs
bs
is misaligned (the memory address in r src1 is not a multiple of 4), the result of
3
0
Initial Values
operation can be used to access the MMIO address aperture (the result of MMIO access by 8- or 16-bit
operation stores all 32 bits of r src2 into the memory locations pointed to by the address in r src1 . The d
operation is a pseudo operation transformed by the scheduler into an
operation optionally takes a guard, specified in r guard . If a guard is present, its LSB controls the
bs)]
bs)]
bs)]
bs)]
r src2 <7:0>
r src2 <15:8>
r src2 <23:16>
r src2 <31:24>
st32 r10 r80
IF r50 st32 r20 r70
IF r60 st32 r30 r70
Operation
PRODUCT SPECIFICATION
[0xd00]
[0xd02]
no change, since guard is false
[0xd04]
[0xd06]
DSPCPU Operations for TM1300
Function unit
Operation code
Number of operands
Modifier
Modifier range
Latency
Issue slots
h_st32d st32d st16 st16d
h_st32d(0)
0x44, [0xd01]
0x22, [0xd03]
0xaa, [0xd05]
0xcc, [0xd07]
st32
ATTRIBUTES
SEE ALSO
Result
st8 st8d
is undefined, and the
0xdd
0x33,
0x11
0xbb,
with the same
st32
st32
dmem
4, 5
n/a
No
31
—
2
A-163
.