tm1300 NXP Semiconductors, tm1300 Datasheet - Page 179

• Manufacturer Part Number: tm1300
• Description: Tm-1300 Media Processor
• Manufacturer: NXP Semiconductors

Philips Semiconductors
12.7
The memory interface consists of 61 signal pins includ-
ing clocks (but excluding power and ground pins).
Table 12-7
Table 12-7. Memory Interface Signal Pins
12.8
Table 12-8
TM1300 data highway bus are mapped to main-memory
address-bus pins (MM_A[13:0]). The mapping is deter-
mined by the state of the rank-size bits in the
MM_CONFIG register.
Table 12-8. Address Mapping Based on Rank Size
The column “Rank Addr./H.Way Bits” specifies which in-
ternal data-highway address bits select the preliminary
SDRAM rank. The actual rank used is subject to the lim-
itation implied by the relationship between SDRAM aper-
ture size (described in
The rank is selected via the chip select bits,
MM_CS#[3:0].
The column “Row Address/H.Way Bits” specifies which
internal data-highway address bits map to the SDRAM
MM_CLK[1:0]
MM_CS#[3..0]
MM_RAS#
MM_CAS#
MM_WE#
MM_A[13:0]
MM_CKE[1:0]
MM_DQM[3:0]
MM_DQ[31:0]
512 KB
16 MB
Rank
1 MB
2 MB
4 MB
8 MB
Size
Name
MEMORY INTERFACE PIN LIST
ADDRESS MAPPING
H.Way
23–22
Addr.
20-19
21-20
22-21
24-23
25-24
Rank
Bits
lists the interface signal pins.
shows how internal address bits from the
13-12
Memory bus clock
Chip selects for the four
memory ranks
Row-address strobe
Column address strobe
Write enable
Address
Clock enable
Byte enables for dq bus
Bi-directional data bus
10–0
10–0
10–0
Pins
6–0
8–0
9–0
12,
8,
Address
Row
Section
Function
H.Way
17–11
19–11
20–11
21–11
22–12
12-11,
23–13
Bits
18,
11,
13.3.1) and the rank size.
Pins
7–0
7–0
7–0
7–0
8–0
9–0
12,
12,
Address
Column
H.Way
10–6,
10–6,
10–6,
10–6,
11–6,
12–6,
Bits
4–2
4–2
4–2
4–2
4–2
4–2
11,
11,
I/O
I/O
O
O
O
O
O
O
O
O
Pin
10
11
11
11
9
9
Address
Active...
Bank
High
High
High
High
High
Low
Low
Low
Low
H.Way
Bit
5
row address. “Row Address/Pins” specifies which lines
of TM1300’s MM_A address bus serve as the SDRAM
row address.
The column ‘Column Address/H.Way Bits’ specifies
which data-highway address bits map to the SDRAM col-
umn address. ‘Column Address/Pins’ specifies which
lines of TM1300’s MM_A address bus serve as the
SDRAM column address.
MM_A[12] is only defined for a 8- or 16-MB rank size.
MM_A[12] contains H.Way bit 11 during the RAS and
CAS operations. MM_A[12] can be used as a bank select
(4-bank SDRAMs) or as a Row address (two bank
SDRAMs).
MM_A[13] is only defined for a 16-MB rank size.
MM_A[13] contains H.Way bit 12 during the RAS opera-
tion. MM_A[13] can only be used as a Row address
Highway address bits 5–0 are the offset within a 64-byte
block. All ‘0’ for an aligned block transfer. Table 12-8 lists
the mapping of bits 5–2 to identify in which SDRAM po-
sitions the words of a block are located. Bit 5 is always
mapped to (one of) the SDRAM internal bank selects;
thus, each SDRAM bank receives half (32 bytes) of the
block transfer.
Highway address bits 4–2 are the word offset in a cache
block. Bits 1–0 are the byte offset within a 32-bit word.
12.9
Immediately after reset, the main-memory interface is ini-
tialized by placing default values in the MM_CONFIG
and PLL_RATIOS registers (see
System
ware boot process, when TM1300 reads initial values
from an external ROM, these registers can be set to dif-
ferent values.
After TM1300 is released from the reset state, the mem-
ory interface automatically executes 10 refresh opera-
tions, then initializes the mode register in each SDRAM
chip.
register(s).
Table 12-9. SDRAM Mode Register Settings
12.10 ON-CHIP SDRAM INTERLEAVING
The main-memory interface (MMI) takes advantage of
the on-chip interleaving of SDRAM devices. Interleaving
allows the precharge, RAS, and CAS commands needed
to access one internal bank to be performed while useful
data transfer is occurring with the other internal bank.
Thus, the overhead of preparing one bank is hidden dur-
ing data movement to or from the other.
PRODUCT SPECIFICATION
Burst length
Wrap type
CAS latency
Table 12-9
MEMORY INTERFACE AND SDRAM
INITIALIZATION
Programming”). During the subsequent hard-
Parameter
shows the settings in the SDRAM mode
SDRAM Memory System
Section 12.6, “Memory
Interleaved
Value
4
3
12-5