tm1300 NXP Semiconductors, tm1300 Datasheet - Page 153

• Manufacturer Part Number: tm1300
• Description: Tm-1300 Media Processor
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Figure 10-4. SPDO unit status/control field MMIO layout.
10.14 MMIO REGISTER DESCRIPTION
Table 10-4. SPDO_STATUS MMIO register
BUF1_EMPTY
BUF2_EMPTY
HBE
UNDERRUN
BUF1_ACTIVE
MMIO_base
0x10 4C00
0x10 4C04
0x10 4C0C
0x10 4C08
0x10 4C10
0x10 4C14
0x10 4C18
field
offset:
type
SPDO_STATUS (r/
SPDO_CTL (r/w)
r/o
r/o
r/o
r/o
r/o
SPDO_FREQ (r/w)
SPDO_BASE1 (r/w)
SPDO_BASE2 (r/w)
SPDO_SIZE (r/w)
SPDO_TSTAMP (r/o)
Sticky flag - set if DMA buffer 1 emp-
tied by the SPDO hardware. Can only
be cleared by software write to
ACK_BUF1.
Sticky flag - set if DMA buffer 2 emp-
tied by the SPDO hardware. Can only
be cleared by software write to
ACK_BUF2.
Highway Bandwidth Error. Sticky flag -
set if internal SPDO buffers emptied
before new data brought from memory.
Refer to
Highway Latency.”
only by a software write to ACK_HBE.
Sticky flag - set if both DMA buffers
were emptied before a new full buffer
was assigned by the DSPCPU. The
hardware has performed a normal
buffer switch over and is emitting old
data. Can only be cleared by software
write to ACK_UDR.
Flag - set if the hardware is currently
emitting DMA buffer 1 data; negated
when emitting DMA buffer 2 data.
TRANS_ENABLE
RESET
TRANS_MODE
Section 10.17, “HBE and
LITTLE_ENDIAN
description
Can be cleared
31
31
31
SLEEPLESS
27
27
27
23
23
23
Table 10-5. SPDO_CTL MMIO register
PRODUCT SPECIFICATION
ACK_BUF1
ACK_BUF2
ACH_HBE
ACK_UDR
BUF1_INTEN
BUF2_INTEN
HBE_INTEN
UDR_INTEN
BASE1
BASE2
19
19
19
field
SIZE (in bytes)
FREQUENCY
TIMESTAMP
15
15
15
type
w/o
w/o
w/o
w/o
r/w
r/w
r/w
r/w
UDR_INTEN
HBE (Highway bandwidth error)
HBE_INTEN
Always reads as ‘0’. Write a ‘1’ here
to clear BUF1_EMPTY. This
informs SPDO that DMA buffer 1 is
now full. Writing a ‘0’ has no effect.
Always reads as ‘0’. Write a ‘1’ here
to clear BUF2_EMPTY. This
informs SPDO that DMA buffer 2 is
now full. Writing a ‘0’ has no effect.
Always reads as ‘0’. Writing a ‘1’
here clears HBE.
Always reads as ‘0’. Writing a ‘1’
here clears UNDERRUN.
If BUF1_EMPTY asserted and this
bit asserted, the SRC 25 interrupt
line is asserted.
If BUF2_EMPTY asserted and this
bit asserted, the SRC 25 interrupt
line is asserted.
If HBE asserted and this bit
asserted, the SRC 25 interrupt line
is asserted.
If UNDERRUN asserted and this bit
asserted, the SRC 25 interrupt line
is asserted.
11
11
BUF2_INTEN
11
BUF1_ACTIVE
BUF1_INTEN
UNDERRUN
ACK_UDR
description
ACK_HBE
7
7
7
ACK_BUF2
BUF2_EMPTY
BUF1_EMPTY
ACK_BUF1
0
0
0
0
0
0
SPDIF Out
3
3
0
0
0
3
0
0
0
0
0
0
10-5
0
0
0
0
0
0