tm1300 NXP Semiconductors, tm1300 Datasheet - Page 335

• Manufacturer Part Number: tm1300
• Description: Tm-1300 Media Processor
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Floating-point compare less-than or equal
pseudo-op for fgeq
SYNTAX
FUNCTION
DESCRIPTION
exchanged (
source files.)
second argument, r src2 ; otherwise, r dest is set to 0. The arguments are treated as IEEE single-precision floating-point
values; the result is an integer. If an argument is denormalized, zero is substituted for the argument before computing
the comparison, and the IFZ flag in the PCSW is set. If
flags in the PCSW are set. The PCSW exception flags are sticky: the flags can be set as a side-effect of any floating-
point operation but can only be reset by an explicit
occurs at the same time as r dest is written. If any other floating-point compute operations update the PCSW at the
same time, the net result in each exception flag is the logical OR of all simultaneous updates ORed with the existing
PCSW value for that exception flag.
modification of the destination register. If the LSB of r guard is 1, r dest and the exception flags in PCSW are written;
otherwise, r dest is not changed and the operation does not affect the exception flags in PCSW.
EXAMPLES
r30 = 0x40400000 (3.0), r40 = 0 (0.0)
r30 = 0x40400000 (3.0)
r10 = 0, r60 = 0x3f800000 (1.0),
r30 = 0x40400000 (3.0)
r20 = 1, r60 = 0x3f800000 (1.0),
r30 = 0x40400000 (3.0)
r30 = 0x40400000 (3.0),
r60 = 0x3f800000 (1.0)
r30 = 0x40400000 (3.0),
r61 = 0xffffffff (QNaN)
r50 = 0x7f800000 (+INF)
r55 = 0xff800000 (-INF)
r60 = 0x3f800000 (1.0),
r65 = 0x00400000 (5.877471754e-39)
r50 = 0x7f800000 (+INF)
The
The
The
The
[ IF r guard ] fleq r src1 r src2
if r guard then {
}
if (float)r src1 <= (float)r src2 then
else
fleq
fleqflags
fleq
r dest
r dest
fleq
Initial Values
fleq
operation sets the destination register, r dest , to 1 if the first argument, r src1 , is less than or equal to the
operation optionally takes a guard, specified in r guard . If a guard is present, its LSB controls the
operation is a pseudo operation transformed by the scheduler into an
1
0
’s r src1 is
operation computes the exception flags that would result from an individual
fgeq
’s r src2 and vice versa). (Note: pseudo operations cannot be used in assembly
fleq r30 r40
fleq r30 r30
IF r10 fleq r60 r30
IF r20 fleq r60 r30
fleq r30 r60
fleq r30 r61
fleq r50 r55
fleq r60 r65
fleq r50 r50
r dest
writepcsw
Operation
fleq
r80
r90
r120
r121
r125
r126
r127
PRODUCT SPECIFICATION
causes an IEEE exception, the corresponding exception
operation. The update of the PCSW exception flags
r100
r110
r80
r90
no change, since guard is false
r110
r120
r121
r125
r126
r127
DSPCPU Operations for TM1300
Function unit
Operation code
Number of operands
Modifier
Modifier range
Latency
Issue slots
0
1
1
0
0, INV flag set
0
0, IFZ flag set
1
ileq fgeq fleqflags
readpcsw writepcsw
fgeq
ATTRIBUTES
SEE ALSO
Result
fleq
with the arguments
.
fcomp
fleq
146
No
—
2
1
3
A-49