tm1300 NXP Semiconductors, tm1300 Datasheet - Page 318

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tm1300

Manufacturer Part Number
tm1300
Description
Tm-1300 Media Processor
Manufacturer
NXP Semiconductors
Datasheet

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Part Number:
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TM1300 Data Book
dspuquadaddui
SYNTAX
FUNCTION
DESCRIPTION
bit bytes of r src1 and r src2 . The bytes in r src1 are considered unsigned values; the bytes in r src2 are considered
signed. The four sums are clipped into the unsigned range [255..0] (or [0xff..0]); thus, the final byte sums are
unsigned. All computations are performed without loss of precision.
the modification of the destination register. If the LSB of r guard is 1, r dest is written; otherwise, r dest is not changed.
EXAMPLES
A-32
r30 = 0x02010001, r40 = 0xffffff01
r10 = 0, r60 = 0x9c9c6464, r70 = 0x649c649c
r20 = 1, r60 = 0x9c9c6464, r70 = 0x649c649c
As shown below, the
The
[ IF r guard ] dspuquadaddui r src1 r src2
if r guard then {
}
r src1
for (i
}
dspuquadaddui
temp
if temp < 0 then
else if temp > 0xff then
else r dest <m:n>
3
unsigned
r dest <m:n>
r dest <m:n>
10-bit signed sums
Four full-precision
0, m
zero_ext8to32(r src1 <m:n>) + sign_ext8to32(r src2 <m:n>)
Initial Values
2
31, n
unsigned
0
0xff
dspuquadaddui
temp<7:0>
24; i < 4; i
operation optionally takes a guard, specified in r guard . If a guard is present, its LSB controls
9
PRODUCT SPECIFICATION
Clip to [255..0]
1
signed
unsigned
r dest
3
i + 1, m
unsigned
0
7
operation computes four separate sums of the four pairs of corresponding 8-
dspuquadaddui r30 r40
IF r10 dspuquadaddui r60 r70
IF r20 dspuquadaddui r60 r70
unsigned
9
Clip to [255..0]
Quad clipped add of unsigned/signed bytes
m – 8, n
signed
2
unsigned
0
0
n – 8) {
1
r dest
9
unsigned
r src2
Operation
Clip to [255..0]
signed
3
signed
7
unsigned
0
r50
2
9
Clip to [255..0]
signed
0
signed
Function unit
Operation code
Number of operands
Modifier
Modifier range
Latency
Issue slots
r80
r90
Philips Semiconductors
1
0
signed
dspidualadd
ATTRIBUTES
r50
no change, since guard is
false
r90
SEE ALSO
0x01000002
0xff38c800
7
Result
signed
dspalu
1, 3
No
78
0
2
2

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