tm1300 NXP Semiconductors, tm1300 Datasheet - Page 163

• Manufacturer Part Number: tm1300
• Description: Tm-1300 Media Processor
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Table 11-6. Base Class Encodings
Table 11-7. Subclass & programming interface fields
bit words. Initiating devices, such as the TM1300, that
can generate memory-write-and-invalidate commands
must implement this register. When implemented, the
cache line size allows initiators participating in the PCI
caching protocol to retry burst accesses at cache-line
boundaries.
This register is implemented in TM1300. In the TM1300,
PCI DMA performs write-and-invalidate cycles as per the
table below. ICP DMA and CPU PCI writes are per-
formed using normal memory-write cycles.
Table 11-8. Cache line size values
11.6.8
The value of the Latency Timer register specifies the
minimum number of PCI clock cycles the TM1300 BIU
(as initiator) is allowed to own the PCI bus. This register
is readable and writable in PCI configuration space.
Cache Line Size
0000,0100
0000,1000
0001,0000
all other values
Base Class
Subclass
(in hex)
(in hex)
0D–FE
00
01
80
(binary)
0A
0B
0C
FF
00
01
02
03
04
05
06
07
08
Latency Timer Register
Interface (in hex)
Device was built before class code definitions
were finalized
Mass-storage controller
Network controller
Display controller
Multimedia device
Memory controller
Bridge device
Simple communications controller
Base system peripheral
Docking station
Processor
Serial bus controller
Reserved
Device does not fit any of the above classes
Programming
write-and-invalidates are done in 4-
DWORD, i.e. 16-byte chunks
write-and-invalidate in 8-DWORD chunks
write-and-invalidate in 16-DWORD chunks
only normal ‘memory-write’ is performed
00
00
00
Video device
Audio device
Other multimedia device
Meaning
Effect
Meaning
Figure 11-6. Header type register format.
This register must be writable in any PCI-initiating device
that can burst more than two data phases. In the TM1300
PCI interface, the least-significant three bits are hard-
wired to ’0’ and software can program any value into the
most-significant five bits. This permits software to specify
the time slice with a minimum granularity of eight PCI
clocks. A value of ’0’ signifies maximum latency, i.e. 256
PCI clocks.
11.6.9
The value of the Header Type register defines the format
of words 16 through 63 in configuration space and
whether or not the device contains multiple functions.
Figure 11-6
Bit 7 of Header Type is ’0’ for single-function devices, ’1’
for multi-function devices. TM1300 is a single-function
device, so bit 7 is ’0’.
the Layout field.
Table 11-9. Layout encodings
11.6.10 Built-In Self Test Register
When implemented, the BIST register is used to control
the operation of a device’s built-in self testing capability.
TM1300 does not implement BIST, so this register is
hardwired to return ’0’s when read.
11.6.11 Base Address Registers
The TM1300 PCI interface implements two configuration
space memory Base Address registers: DRAM_BASE
and MMIO_BASE. DRAM_BASE relocates TM1300’s
SDRAM within the system address space; MMIO_BASE
relocates the 2-MB memory-mapped I/O address aper-
ture.
The values in the Base Address registers determine the
address map as seen by both the DSPCPU and external
PCI masters. These values are normally set once, and
not changed dynamically once the DSPCPU operates.
Hardware RESET initializes DRAM_BASE to 0x0 and
MMIO_BASE to 0xefe0,0000, after which the TM1300
boot protocol sets the final value.
In standalone systems, the autonomous boot sequence
is executed. In this case, the values of DRAM_BASE and
MMIO_BASE are copied from the content of the serial
boot EEPROM, as described in
DSPCPU Program Load for Autonomous Bootstrap.”
PRODUCT SPECIFICATION
Header Type
Layout (in hex)
00
01
Header Type Register
shows the format of Header Type.
MF
7
Table 11-9
6
Non-bridge PCI device
PCI-to-PCI bridge device
shows the encodings of
Section 13.3.2, “Initial
Layout
Meaning
PCI Interface
11-7
0