tm1300 NXP Semiconductors, tm1300 Datasheet - Page 181

• Manufacturer Part Number: tm1300
• Description: Tm-1300 Media Processor
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Table 12-11. Glueless interface limits for address/
clocks
• Signal traces between TM1300 and the memory
• The clock-signal trace(s) should be as short as pos-
• Address and control-signal traces should also be
• Data-signal traces should also be short, but their
• Connections to several loads should follow a “T” con-
12.15.2 Specific Guidelines
• The maximum length for a signal trace is 10 cm. For
• The maximum capacitive load is 30 pF per trace,
• The signal traces on the TM1300 circuit board must
• At most two SDRAM devices may be connected to
Figure 12-4. Conceptual board layout.
capacitance. Close proximity is especially important
for a 143-MHz memory system.
chips should be matched in length as closely as pos-
sible to minimize signal skew.
sible.
short, but their length is less critical than the clock’s.
length is less critical than the clock’s, especially if
only one or two ranks are connected.
nection scheme in order to limit the reflections.
143-MHz operation, signal trace length should not be
longer than 7 cm.
including loads.
be designed as 50-ohm transmission lines.
each MM_CLK signal at 143 MHz.
Memory Chips
4
6
8
DSPCPU
TM1300
Peripherals
On-Chip
Highway
Data
Maximum Clock Frequency
Interface
TM1300
Memory
143 MHz
133 MHz
133 MHz
RAS#, CAS#, WE#
Clock Enables,
Data[31:0]
Address,
Clock
33
12.15.3 Termination
No termination is required for address, data, and control
signals. Address and control signals are driven only by
TM1300; the output impedance of the drivers is suffi-
ciently matched to prevent excessive ringing. TM1300
design assumes that when driving data lines, the output
drivers of SDRAM chips are also sufficiently impedance
matched.
Series termination of the clock outputs with a 33-ohm re-
sistor is advised.
12.16 TIMING BUDGET
The glueless interface of the TM1300 main-memory in-
terface makes the memory system simple and straight-
forward from one point of view, but to ensure reliable op-
eration at high clock rates, system designers must follow
the board design guidelines (see
Board
SDRAM devices must meet the critical specifications list-
ed in
MHz (T
Table 12-12. Required SDRAM performance for 143-
MHz memory system
These values leave virtually no margin for the critical tim-
ing parameters in a high-speed system and assume a to-
tal worst case delay of 0.5 ns for the board traces (T
PRODUCT SPECIFICATION
Max. output delay
Min. output hold time
Max. input setup time
Max. input hold time
Table 12-12
Design”).
cycle
Timing Parameter
= 7 ns) memory system.
to ensure reliable operation of an 143-
t
t
t
t
AC
OH
IS
IH
SDRAM Memory System
Section 12.15, “Circuit
SDRAM
Device
SDRAM
Device
6.0 ns
2.0 ns
2.0 ns
1.0 ns
Value
board
12-7
)