tm1300 NXP Semiconductors, tm1300 Datasheet - Page 173

• Manufacturer Part Number: tm1300
• Description: Tm-1300 Media Processor
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Figure 11-13. Back-to-back PCI burst write operations with 16 data phases which might be generated by the
ICP when writing image data to a PCI-resident video frame buffer.
Figure 11-13
transfers. The ICP is capable of exploiting the high band-
width available with back-to-back DMA operations when
it is writing image data to a frame buffer on a PCI video
card.
The timing of
granted to TM1300 until at least the beginning of the sec-
ond DMA burst operation. For as long as bus ownership
is granted to TM1300 and the ICP has queued requests
for data transfer, the PCI interface will perform back-to-
back DMA operations. If the target eventually becomes
unable to accept more data, it signals a disconnect on
the TM1300 PCI interface. The PCI interface remembers
where the DMA burst was interrupted and attempts to re-
start from that point after two bus clocks.
11.9
11.9.1
The PCI interface does not implement lock#, sbo, and
sbone pins. Consequently, it is possible for both the
DSPCPU and external PCI initiators to write to a critical
memory section simultaneously. Software must imple-
ment policies to guarantee memory coherency.
LIMITATIONS
Bus Locking
devsel#
frame#
pci_clk
c/be#
Figure 11-13
illustrates back-to-back DMA burst data
trdy#
irdy#
ad
1
assumes that the PCI bus is
Command
Address
2
Data 1
3
Byte Enables
Data 15
18
Data 16
11.9.2
TM1300 does not implement the PCI expansion ROM
capability.
11.9.3
The PCI interface does not implement the PCI cacheline-
wrap address mode for external PCI initiators that ac-
cess TM1300 SDRAM.
11.9.4
Only single-data-phase transactions to configuration and
I/O spaces are supported. The byte-enable signals se-
lect the byte(s) within the addressed word.
11.9.5
External initiators can access TM1300 MMIO registers
only as full words. The byte-enable signals have no ef-
fect on the data transferred. External initiators must read
and write all four bytes of MMIO registers.
PRODUCT SPECIFICATION
19
Data 17
20
No Expansion ROM
No Cacheline Wrap Address
Sequence
No Burst for I/O or Configuration
Space
Word-Only MMIO Register Access
Byte Enables
Data 31
35
Data 32
36
PCI Interface
11-17