tm1300 NXP Semiconductors, tm1300 Datasheet - Page 293

• Manufacturer Part Number: tm1300
• Description: Tm-1300 Media Processor
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Arithmetic shift left
SYNTAX
FUNCTION
DESCRIPTION
and r dest is set to r src1 arithmetically shifted left by this amount. If the rsrc2<31:5> value is not zero, then take this as
a shift by 32 or more bits. Zeros are shifted into the LSBs of r dest while the MSBs shifted out of r src1 are lost.
modification of the destination register. If the LSB of r guard is 1, r dest is written; otherwise, r dest is unchanged.
EXAMPLES
r60 = 0x20, r30 = 3
r10 = 0, r60 = 0x20, r30 = 3
r20 = 1, r60 = 0x20, r30 = 3
r70 = 0xfffffffc, r40 = 2
r80 = 0xe, r50 = 0xfffffffe
r30 = 0x7008000f, r60 = 0x20
r30 = 0x8008000f, r45 = 0x80000000
r30 = 0x8008000f, r45 = 0x23
As shown below, the
The
[ IF r guard ] asl r src1 r src2
if r guard then {
}
r src1
n
r dest <31:n>
r dest <n–1:0>
if rsrc2<31:5> != 0 {
}
rdest <- 0
asl
3
r src2 <4:0>
Initial Values
operation optionally takes a guard, specified in r guard . If a guard is present, its LSB controls the
Intermediate result
r src1 <31–n:0>
0
(example: n = 3)
asl
operation takes two arguments, r src1 and r src2 . R src2 specify an unsigned shift amount,
r dest
asl r60 r30
IF r10 asl r60 r30
IF r20 asl r60 r30
asl r70 r40
asl r80 r50
asl r30 r60
asl r30 r45
asl r30 r45
3
r dest
32 bits from r src1
Operation
0
r90
r120
r125
r111
r100
r100
Left shifter
PRODUCT SPECIFICATION
r src2
r100
r110
3
r90
no change, since guard is false
r110
r120
r125
r111
r100
r100
3
0
0
DSPCPU Operations for TM1300
0x100
0
0
0x100
0xfffffff0
0x00000000 (shift by more than 32)
0x00000000
0x00000000
0x00000000
0
0
0
asli asr asri lsl lsli lsr
Function unit
Operation code
Number of operands
Modifier
Modifier range
Latency
Issue slots
lsri rol roli
Result
ATTRIBUTES
SEE ALSO
r src2
shifter
1, 2
No
19
—
0
2
1
asl
A-7