tm1300 NXP Semiconductors, tm1300 Datasheet - Page 176

• Manufacturer Part Number: tm1300
• Description: Tm-1300 Media Processor
• Manufacturer: NXP Semiconductors

TM1300 Data Book
12.4
The devices and organizations supported can be config-
ured as listed in
LVTTL, 3.3-V interface.
Table 12-2. Supported Rank Configurations
Refer to
evaluate the support of 2-bank, 64-Mbit devices. These
devices are not widely used and not described in the fol-
lowing sections.
12.4.1
TM1300 supports synchronous DRAM chips directly.
SDRAM has a fast, synchronous interface that permits
burst transfers at 1 word per clock cycle. The memory in-
side an SDRAM device is divided into two or four banks;
the SDRAM implements interleaved bank access to sus-
tain maximum bandwidth.
SDRAM devices implement a power down mechanism
with self-refresh. TM1300’s power management takes
advantage of this mechanism.
12-2
Figure 12-1. A high-performance memory interface connects the TM1300 internal highway bus to external
SDRAM or SGRAM. The interface is glueless for an array of up to four devices.
a.
b.
Device Size
(Mbit)
128
128
Limited support for a 32-MB configuration only.
However MM_CONFIG.SIZE is 16 MB (i.e. 6).
16
64
2
4
8
MEMORY DEVICES SUPPORTED
a
Section 12.8, “Address Mapping,”
SDRAM
DSPCPU
TM1300
Peripherals
2
2
2
2
2
2
2
4
4
4
4
4
On-Chip
Table
64K
128K
128K
256K
512K
1M
2M
512K
1M
2M
1M
2M
Device(s)
8 SDRAM
4 SDRAM
16 SDRAM
8 SDRAM
32 SDRAM
16 SDRAM
12-2. All devices must have a
Highway
16 SDRAM
Data
16 SDRAM
32 SGRAM
32 SGRAM
16 SDRAM
32 SDRAM
PRODUCT SPECIFICATION
Interface
TM1300
Memory
a
RAS#, CAS#, WE#
Byte Enables[3:0]
Clock Enables,
Chip Selects#
Rank Size
Data[31:0]
Address,
512 KB
32
32
16 MB
16 MB
16 MB
1 MB
1 MB
2 MB
4 MB
8 MB
8 MB
in order to
b
b
Clock
MB
MB
33
TM1300 supports only Jedec-compatible SDRAM with
two or four internal banks of memory per device.
12.4.2
Also supported in TM1300 systems, SGRAM is essen-
tially an SDRAM with additional features for raster graph-
ics functions. The device type is standardized by Jedec
and offered by multiple DRAM vendors. Tying the DSF
input of an SGRAM low makes the device operates like
a standard 32-bit-wide SDRAM and thus compatible with
the TM1300 memory interface.
12.5
TM1300 supports a variety of memory sizes thanks to:
• Many possible configurations of SDRAM devices
• Support for up to four memory ranks
The minimum memory size is 512 KB using two
2 64K 16 SDRAM devices on the 32-bit data bus. Up to
four memory devices can be connected without any glue
logic and without sacrificing performance. The maximum
memory size with full performance is 32 MB using four
4 1M 16 SDRAM chips, four 4 x 512K x 32, or two
8 1M 16 on a 32-bit data bus.
Larger memories can be constructed using more devic-
es. To do so, the frequency of the memory interface must
be lowered to account for extra propagation delay due to
the excessive loading on the interface signals (see
tion 12.13, “Output Driver
The following rules apply to memory rank design:
• All devices in a rank must be of the same type.
• All ranks must be a power of two in size.
• All ranks must be of equal size.
Table 12-3
Refer to the TM1100 Databook for smaller memory con-
figurations. Note:
• Some of these configurations may not be economi-
• ‘Max. MHz’ refers to the memory interface/SDRAM
cally attractive due to the price premium.
speed, not the TM1300 core operating frequency.
MEMORY GRANULARITY AND SIZES
SGRAM
lists some example memory system designs.
CS#
Address, Control
DQM[3:0]
CLK
DQ[31:0]
Capacity”).
Philips Semiconductors
SDRAM
Memory
Array
Sec-