tm1300 NXP Semiconductors, tm1300 Datasheet - Page 132

• Manufacturer Part Number: tm1300
• Description: Tm-1300 Media Processor
• Manufacturer: NXP Semiconductors

TM1300 Data Book
8.3
Figure 8-1
AI unit. At the heart of the clock system is a square wave
DDS (Direct Digital Synthesizer). The DDS can be pro-
grammed to emit frequencies from approx. 1 Hz to 40
MHz with a resolution of better than 0.3 Hz.
The output of the DDS is always sent on the AI_OSCLK
output pin. This output is intended to be used as the
256f
quency crystal for oversampling A/D converters, such as
the Philips SAA7366T, or Analog Devices AD1847.
The TM1300 AI DDS frequency is set by writing to the
FREQUENCY MMIO register. The programmer can
change the FREQUENCY setting dynamically, so as to
adjust the input sampling rate to track an application de-
pendent master reference.
Depending on bit 31 (MSB), the DDS runs in one of two
modes:
• bit 31 = 1 (TM1300 improved mode)
• bit 31 = 0 (TM1000 compatibility mode)
8.3.1
In improved mode, a high quality, low-jitter AI_OSCLK is
generated. The setting of the FREQUENCY register to
accomplish a given AI_OSCLK frequency is given by:
This mode, and the above formula, should be used for all
new software development on TM1300. It is not available
on TM1000.
8.3.2
TM1000 compatibility mode is provided so that TM1000
software runs without changes. It should NOT be used
for new TM1300 software development. TM1000 mode
is automatically entered whenever FREQUENCY[31] =
0. In TM1000 mode, AI_OSCLK frequency is set as fol-
lows:
8-2
Figure 8-1. AI clock system and I/O interface.
FREQUENCY
s
AI_OSCLK
or 384f
AI_SCK
AI_WS
CLOCK SYSTEM
AI_SD
TM1300 Improved Mode
TM1000 Compatibility Mode
illustrates the different clock capabilities of the
(e.g. 256 f
(e.g. 64 f
s
system clock source instead of a fixed fre-
s
s
)
)
=
2
31
PRODUCT SPECIFICATION
Serial To Parallel Converter
+
------------------------------- -
9 f
f
OSCLK
DSPCPU
div N+1
div N+1
SER_MASTER
2
32
8
7
16
16
WSDIV
SCKDIV
LEFT[15:0]
RIGHT[15:0]
sample_clock
8.4
AI_SCK and AI_WS can be configured as input or out-
put, as determined by the SER_MASTER control field.
As output, AI_SCK is a divider of the DDS output fre-
quency. Whether input or output, the AI_SCK pin signal
is used as the bit clock for serial-parallel conversion.
If set as output, AI_WS can similarly be programmed us-
ing WSDIV to control the serial frame length from 1 to
512 bits.
Table 8-2. Sample rate settings (f
MHz, improved TM1300 mode)
The preferred application of the clock system options is
to use AI_OSCLK as A/D master clock, and let the A/D
converter be timing master over the serial interface
(SER_MASTER=0).
In case an external codec (e.g. the AD1847 or CS4218)
is used for common audio I/O, it may not be possible to
independently control the A/D and D/A system clocks. In
that case it is recommended that the Audio Out (AO) unit
clock system DDS is used to provide a single master A/
D and D/A clock. The AO unit, or the D/A converter, can
be used as serial interface timing master, and the AI unit
is set to be slave to the serial frame determined by AO
9 DSPCPUCLK
44.1 kHz
48.0 kHz
44.1 kHz
48.0 kHz
f
AISCK
0
0
f
s
FREQUENCY
CLOCK SYSTEM OPERATION
=
31
---------------------------------- -
SCKDIV
OSCLK
f AI
256f
256f
384f
384f
OSCLK
s
s
s
s
+
=
Square Wave DDS
1
SCK
64f
64f
64f
64f
FREQUENCY
------------------------------- -
Philips Semiconductors
3 f
f
s
s
s
s
OSCLK
SCKDIV
DSPCPU
FREQUENCY
2187991971
2191574340
2208246133
2213619686
DSPCPUCLK
2
32
[ ,
0 255
=133
SCKDIV
]
0
3
3
5
5