tm1300 NXP Semiconductors, tm1300 Datasheet - Page 157

• Manufacturer Part Number: tm1300
• Description: Tm-1300 Media Processor
• Manufacturer: NXP Semiconductors

PCI Interface
11.1
TM1300 DMA read transactions use the more efficient
‘memory read multiple’ PCI transactions, unless explicit-
ly disabled.
TM1300 contains an on-board PCI_CLK generator for
low-cost configurations. It can be enabled/disabled at
boot time. See
TM1300 has a sideband control signal that allows glue-
less connection of simple slave peripherals directly to the
PCI bus wires. This can be used to connect Flash, ROM,
SRAM, UARTs, etc. with 8-bit data and demultiplexed
addresses. Refer to
Bus.”
11.2
TM1300 includes a PCI interface for easy integration into
personal computer applications—where the PCI-bus is
the standard for high-speed peripherals. In embedded
applications, with TM1300 serving as the main CPU, the
PCI bus can interface to peripheral devices that imple-
ment functions not provided by the on-chip peripherals.
See
The main function of the PCI interface is to connect the
TM1300 on-chip highway and PCI buses. A bus cycle on
the internal highway that targets an address mapped into
PCI space will cause the PCI interface to create a PCI
bus cycle. Similarly, a bus cycle on PCI that targets an
address mapped into TM1300 memory space will cause
the PCI interface to create a highway bus cycle targeted
at SDRAM. For some operations, the PCI interface is ex-
plicitly programmed by the DSPCPU.
Figure 11-1. Two typical system implementations: (a) shows TM1300 as a PCI peripheral in a desktop PC, (b)
shows an embedded system with TM1300 as the host CPU.
Figure
PCI Agent
NEW IN TM1300
PCI OVERVIEW
TM1300
11-1.
Section
Section
PCI Bus
a) TM1300 as peripheral
11.7.5.
Chapter 22, “PCI-XIO External I/O
13.2.
Controller
Interrupt
PCI Agent
PCI Bridge
PCI Bus
Arbiter
(e.g., x86)
Host CPU
PCI Agent
by Gert Slavenburg, Ken-Sue Tan, Babu Kandimalla
From TM1300, only the DSPCPU and the image copro-
cessor (ICP) unit can cause the PCI interface to create
PCI bus cycles; the other on-chip peripherals cannot see
external hardware through the PCI interface. From PCI,
SDRAM and most of the registers in MMIO space can be
accessed by external PCI initiators.
The PCI interface implements DMA (also called block or
burst) and non-DMA transfers. DMA transfers are inter-
ruptible on 64-byte boundaries. The PCI interface can
service outbound (TM1300
TM1300) data flows simultaneously.
Table 11-1
Table 11-1. PCI interface characteristics
PRODUCT SPECIFICATION
PCI Compliance
PCI Speed
Data bus width
Address space
Voltage levels
Burst mode
Posted write
PCI ‘special cycle’
PCI ‘memory write &
invalidate’
PCI ‘interrupt acknowl-
edge’
PCI ‘dual-address
cycle’
PCI Agent
Characteristic
TM1300
lists some of the features of the PCI interface.
PCI Bus
b) TM1300 as host CPU
PCI Bus
Arbiter
PCI Agent
PCI Local Bus Specification Rev. 2.1
Up to 33 MHz
32-bit only
32 bits (4 GB)
Drive & receive at either 3.3 V or 5V
Yes, w/ double buffering so maxi-
mum transfer rate (132 MB/sec) is
sustainable
Yes, can be disabled
Not recognized
Supported for TM1300 as initiator
Not generated
Not generated
Chapter 11
PCI) and inbound (PCI
Comments
PCI Agent
11-1