tm1300 NXP Semiconductors, tm1300 Datasheet - Page 238

• Manufacturer Part Number: tm1300
• Description: Tm-1300 Media Processor
• Manufacturer: NXP Semiconductors

TM1300 Data Book
transfer, the DSPCPU must refrain from writing to the
IIC_AR.COUNT bitfield until a message is complete.
Completion is indicated by the RBC bitfield decrementing
to zero.
16.4.4
The I
quired for enabling
enable and clear interrupt sources which normally occur
during
scribed in the section on the IIC_SR register are enabled
and cleared through the IIC_CR register. The enable bit-
fields are:
16-4
27:26
Bits
21:6
31
30
29
28
25
24
23
22
10
7
2
C control register contains control information re-
I
SW_MODE_EN 0 (power-on/reset default) - Normal
2
SDNACK_IEN
CLRSANACKI
CLRSDNACKI
SANACK_IEN
C
Field Name
Reserved1
Reserved2
SDA_OUT
IIC_CR Register
CLRGDI
GD_IEN
F_IEN
CLRFI
operation. The four interrupt sources de-
Table 16-7. IIC_CR Register
I
2
C
transfers. This register is used to
Enable for normal transfer complete
interrupt
Enable for IIC_DR data service
request interrupt
Enable for slave address not
acknowledged interrupt
Enable for slave data not acknowl-
edged interrupt. An addressed slave
receiver has refused to accept the
last byte transmitted to it
Always write ‘0’s to these bits.
(See Note1)
Clear bit for the GDI interrupt in the
IIC_SR register. Writing a ‘1’ to this
bit clears the GDI interrupt
Clear bit for the FI interrupt in the
IIC_SR register. Writing a ‘1’ to this
bit clears the FI interrupt
Clear bit for the SANACKI interrupt
in the IIC_SR register. Writing a ‘1’ to
this bit clears the SANACKI interrupt.
Clear bit for the SDNACKI interrupt
in the IIC_SR register. Writing a ‘1’ to
this bit clears the SDNACKI inter-
rupt.
Always write ‘0’s to these bits.
(See Note1)
I2C hardware operating mode.
1 - Enable software operating mode.
The I
by user writes to the ‘sda_out’ and
‘scl_out’ register bits.
Enabled by sw_mode_en. This bit is
used by sw to manually control the
external I
ity is:
1 = SDA pad pulled low
0 = SDA pad left open drain
PRODUCT SPECIFICATION
2
C pins are entirely controlled
2
C SDA data pin. Bit polar-
Definition
• GD_IEN — Enable for normal transfer complete
• F_IEN — Enable for IIC_DR data service request
• SANACK_IEN — Enable for slave address not
• SDNACK_IEN — Enable for slave data not acknowl-
In addition to the interrupt enable bits, the IIC_CR con-
tains interrupt clear bits associated with each of the inter-
rupt sources in the IIC_SR register. These IIC_CR inter-
rupt clear bits are defined as:
• CLRGDI — Clear bit for the GDI interrupt in the
• CLRFI — Clear bit for the FI interrupt in the IIC_SR
• CLRSANACKI — Clear bit for the SANACKI interrupt
• CLRSDNACKI — Clear bit for the SDNACKI interrupt
The remaining bitfield of the IIC_CR register is:
• ENABLE — Master enable for I
16.5
I
ware I
case, the SCL and SDA pins are fully controlled and ob-
2
Bits
C software operation mode is intended for use by soft-
5:2
6
1
0
interrupt.
interrupt.
acknowledged interrupt. This is an error interrupt.
edged interrupt. An addressed slave receiver has
refused to accept the last byte transmitted to it. This
is handled as an error interrupt.
IIC_SR register. Writing a ‘1’ to this bit clears the GDI
interrupt.
register. Writing a ‘1’ to this bit clears the FI interrupt.
in the IIC_SR register. Writing a ‘1’ to this bit clears
the SANACKI interrupt.
in the IIC_SR register. Writing a ‘1’ to this bit clears
the SDNACKI interrupt.
ENABLE must be set equal to ‘1’ to transfer any bits
from the I
ENABLE bit effectively resets the entire I
including all status and interrupt flag bits. A transfer
in progress is aborted and the byte currently trans-
ferred is lost.
Note: For writes, Reserved1, 2, 3 and 4 bitfields
MUST always be written with ‘0’s.
2
C or similar algorithm implementations. In this
I
Table 16-7. IIC_CR Register (Continued)
2
Field Name
Reserved3
Reserved4
C SOFTWARE OPERATION MODE
SCL_OUT
ENABLE
2
C interface block. Writing a ‘0’ to the
Enabled by sw_mode_en. This bit is
used by sw to manually control the
external I
ity is:
1 = SCL pad pulled low
0 = SCL pad left open drain
Always write ‘0’s to these bits.
(See Note1)
Always write ‘0’s to these bits.
(See Note1)
I
2
C serial interface enable
Philips Semiconductors
2
C SCL clock pin. Bit polar-
Definition
2
C serial interface.
2
C interface,