tm1300 NXP Semiconductors, tm1300 Datasheet - Page 172

• Manufacturer Part Number: tm1300
• Description: Tm-1300 Media Processor
• Manufacturer: NXP Semiconductors

TM1300 Data Book
Figure 11-10. Basic single-data-phase read opera-
asserts the frame# signal to indicate that the transaction
has begun and that an address and command are stable
on ad and c/be#, respectively.
TM1300 then releases the ad bus, deasserts frame#, as-
serts irdy#, asserts byte enables on c/be#, and waits for
the target to claim the transaction by asserting devsel#.
The target asserts trdy# to signal the master that the ad
bus contains stable data. The assertion of trdy# causes
the initiator (TM1300 in this case) to sample the ad bus
data and deassert irdy# to complete the single-data-
phase read transaction.
Figure 11-11
eration. The operation begins like a read: TM1300 as-
serts the frame# signal and drives the ad bus with the tar-
get address and drives the command onto the c/be# bus.
The operation continues when TM1300 deasserts
frame#, asserts irdy#, and drives the byte enables as be-
fore, but it also drives the data to be written on the ad
bus. The target device asserts devsel# to claim the trans-
action. Eventually, the target asserts trdy# to signal that
it is sampling the data on the ad bus. TM1300 continues
to drive the data on the ad bus until after the target deas-
serts trdy#, which completes the write operation.
Figure 11-12. PCI burst write operation with 16 data phases.
11-16
devsel#
frame#
pci_clk
c/be#
irdy#
trdy#
ad
shows a typical single-data-phase write op-
1
devsel#
frame#
pci_clk
c/be#
trdy#
irdy#
Command
ad
Address
2
PRODUCT SPECIFICATION
1
Byte Enables
3
Command
Address
2
Data
4
Data 1
3
Data 2
4
Data 3
5
Figure 11-11. Basic single-data-phase write opera-
11.8.2
As with the single-data-phase operations, DMA opera-
tions begin with the assertion of frame# and valid ad-
dress and command information. See
target knows a burst is requested because frame# re-
mains asserted when irdy# becomes asserted.
In the example timing of
ceiving the burst from TM1300. The target asserts
devsel# and trdy# simultaneously. The trdy# signal re-
mains asserted while TM1300 sends a new word of data
on each PCI clock cycle. The burst operation shown is a
16-word burst transfer. Since only the starting address is
sent by the initiator, both initiator and target must incre-
ment source and destination addresses during the burst.
The initiator signals the end of the burst of data in
Figure 11-12
last word (or partial word) of data is transferred in the
clock cycle after frame# is deasserted. Finally, the target
acknowledges the last data phase by deasserting trdy#
and devsel#.
devsel#
Byte Enables
frame#
pci_clk
c/be#
irdy#
trdy#
Data 4
ad
6
Multi-Data-Phase Operations
when it deasserts frame# in clock 17. The
1
Command
Address
Data 15
2
17
Figure
Philips Semiconductors
Data 16
3
18
11-12, a fast device is re-
Byte Enables
Data
Figure
11-12. The
n