tm1300 NXP Semiconductors, tm1300 Datasheet - Page 170

• Manufacturer Part Number: tm1300
• Description: Tm-1300 Media Processor
• Manufacturer: NXP Semiconductors

TM1300 Data Book
Following are descriptions of the fields of IO_CTL and a
discussion of how a DSPCPU write to IO_CTL triggers I/
O cycles.
BE (Byte enables). The BE field (the four least-signifi-
cant bits of IO_CTL) determines the state of PCI’s 4-line
c/be# bus during the data phase of an I/O cycle. Since
the c/be# bus signals are active low, a ‘0’ in a BE field bit
means ‘byte participates;’ a ‘1’ in a BE field bit means
‘byte does not participate.’
spondence between BE bits and bytes on the PCI bus
assuming little-endian byte order .
RW (Read/Write). The RW field (bit 4 of IO_CTL) deter-
mines whether the I/O cycle will be a read or a write.
Table 11-16
1
A write by the DSPCPU to the IO_CTL register starts an
I/O cycle on the PCI bus. The IO_DATA (for a write) and
IO_ADR registers must be set up before writing to
IO_CTL.
During an I/O read, the PCI interface drives the PCI bus
with the address from IO_ADR and the BE field from
IO_CTL. The returned data is buffered in IO_DATA.
When the data is returned, the PCI interface will gener-
ate a DSPCPU interrupt if the appropriate IntE bit is set
in BIU_CTL. Alternatively, DSPCPU software can poll
the appropriate ‘done’ status bit in BIU_STATUS. Finally,
DSPCPU software reads the IO_DATA register in MMIO
space to access the data returned from the I/O cycle.
A write operation proceeds as for a read, except that PCI
data is driven from IO_DATA during the transaction and
no data is returned in IO_DATA.
11.7.14 SRC_ADR Register
The 32-bit SRC_ADR register is used to set the source
address for a block transfer DMA operation. The address
in SRC_ADR must be word (4-byte) aligned, i.e. the 2
LSBs have to be ‘0’. The content of this register during or
after DMA is not defined, hence it cannot be used to track
progress or verify completion of a DMA transaction.
11.7.15 DEST_ADR Register
The 32-bit DEST_ADR register is used to set the desti-
nation address for a block transfer DMA operation. The
address is DEST_ADR must be word (4 byte) aligned,
i.e. the 2 LSBs must be ‘0’. The content of this register
during or after DMA is not defined, hence it cannot be
used to track progress or verify completion of a DMA
transaction.
11.7.16 DMA_CTL Register
A write by the DSPCPU to the DMA_CTL register starts
a DMA block transfer on the PCI bus. The SRC_ADR
and DEST_ADR registers must be set up before writing
to DMA_CTL.
The steps involved in a DMA transfer are:
1. Wait until BIU_STATUS dma_cycle.Busy is de-assert-
11-14
ed
read).
shows the interpretation of RW (0
Table 11-15
PRODUCT SPECIFICATION
shows the corre-
write,
2. Write to SRC_ADR and DEST_ADR as described
3. Write to DMA_CTL to start the DMA transaction.This
4. Wait (polling or interrupt based) until dma_cycle.Done
5. Clear dma_cycle.Done by writing a ‘1’ to it
The fields of DMA_CTL are described below.
TL (Transfer length). The TL field (bits 0..25 of
DMA_CTL) specifies the number of data bytes to be
transferred during the DMA operation. It must be a mul-
tiple of 4 bytes. The maximum length of a DMA operation
is limited to 64 MB, the maximum amount of SDRAM
supported by TM1300. The content of this field during or
after a DMA transaction is not defined.
D (DMA direction). The D field (bit 26 of DMA_CTL) de-
termines the direction of data movement during the block
transfer.
field.
Table 11-17. D interpretation
T (DMA Transaction type). The T field (bit 27 of
DMA_CTL) determines the transaction type of a write, as
described below.
Table 11-18. T interpretation
TM1300 generates memory write-and-invalidate PCI
transactions if all conditions below are satisfied, other-
wise it generates regular memory write transactions:
• The MWI bit in the Command Register is set.
• The Cache Line Size register is set to 4,8, or 16 32-
• The DMA source address is 64 byte aligned.
• The DMA destination address is cache line size
• The T bit is set
TM1300 generates ‘memory read multiple’ PCI transac-
tions for DMA reads, unless the RMD (Read Multiple Dis-
able) bit is set in BIU_CTL, in which case the less effi-
cient ‘memory read’ transactions are used.
During a PCI
drives the PCI bus with the address from SRC_ADR. The
returned data is buffered in r_buffer. The PCI interface
then drives the address from DEST_ADR and the data
from r_buffer to the SDRAM controller. SRC_ADR and
DEST_ADR are incremented, the TL field in DMA_CTL
above
action sets dma_cycle.Busy
is asserted by the hardware
bit words.
aligned.
D
0
1
T
0
1
SDRAM
PCI memory space
memory write
memory write-and-invalidate
Table 11-17
SDRAM block transfer, the PCI interface
PCI memory space (DMA write)
DMA Write transaction type
Data Movement Direction
(shows the interpretation of the D
Philips Semiconductors
SDRAM (DMA read)