r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 1040

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

Section 23 Gigabit Ethernet Controller (GETHER)
23.4.8
Interrupt Processing
(1)
Interrupt Sources
The GETHER issues three types of interrupts to the CPU: receive/transmit interrupts for port 0
(GEINT0), receive/transmit interrupts for port 1 (GEINT1) and transfer interrupts between port 0
and port 1 (GEINT2). Table 23.7 shows these three interrupts, the interrupt sources, interrupt
status registers/bits set at interrupt occurrence, and interrupt generation timing.
GEINT0 or GEINT1 interrupts are generated in correspondence with the port 0 or port 1
transmit/receive operation. When an interrupt source is generated, it is set in EESR0 or EESR1
and an interrupt is issued to the CPU. For some interrupt sources, the EESR0/EESR1 setting and
an interrupt to the CPU are performed after a write-back operation to a descriptor is completed,
not immediately after the interrupt source is detected. Interrupt sources other than the E-MAC
status register source (ECI bit) are cleared by writing a 1 to the corresponding source bit. The E-
MAC status register source (ECI bit) is cleared by writing a 1 to the corresponding source bit in
ECSR. Interrupt source bits retain the values until they are cleared. GEINT0 or GEINT1 interrupt
source is allowed to issue interrupts by setting the corresponding bit in EESIPR0 or EESIPR1.
Each E-MAC state register source (ECI bit) is allowed to issue an interrupt by setting the
corresponding bit in ECSIPR. In the initial value, interrupts are disabled.
GEINT2 interrupt is issued in correspondence with relay operation between port 1 and port 0.
When an interrupt source is generated, it is set to the corresponding bit in TSU_FWSR and an
interrupt is issued to the CPU. Each GEINT2 interrupt source is cleared by writing a 1 to the
corresponding bit. The interrupt source bit retains the value until it is cleared. Each GEINT2
interrupt source is allowed to issue an interrupt by setting the corresponding bit in TSU_FWSR. In
the initial state, interrupts are disabled.
Table 23.7 shows these three interrupts, interrupt sources, interrupt status registers and bits set at
interrupt occurrence and interrupt generation timing.
Rev. 1.00 Oct. 01, 2007 Page 974 of 1956
REJ09B0256-0100