r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 200

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

Section 5 Exception Handling
• Indivisible delayed branch instruction and delay slot instruction
Rev. 1.00 Oct. 01, 2007 Page 134 of 1956
REJ09B0256-0100
With MAC instructions, memory-to-memory arithmetic/logic instructions, TAS instructions,
and MOVUA instructions, two data transfers are performed by a single instruction, and an
exception will be detected for each of these data transfers. In these cases, therefore, the
following order is used to determine priority.
1. Data address error in first data transfer
2. TLB miss in first data transfer
3. TLB protection violation in first data transfer
4. Initial page write exception in first data transfer
5. Data address error in second data transfer
6. TLB miss in second data transfer
7. TLB protection violation in second data transfer
8. Initial page write exception in second data transfer
As a delayed branch instruction and its associated delay slot instruction are indivisible, they
are treated as a single instruction. Consequently, the priority order for exceptions that occur in
these instructions differs from the usual priority order. The priority order shown below is for
the case where the delay slot instruction has only one data transfer.
1. A check is performed for the interrupt type and re-execution type exceptions of priority
2. A check is performed for the interrupt type and re-execution type exceptions of priority
3. A check is performed for the completion type exception of priority level 2 in the delayed
4. A check is performed for the completion type exception of priority level 2 in the delay slot
5. A check is performed for priority level 3 in the delayed branch instruction and priority
6. A check is performed for priority level 4 in the delayed branch instruction and priority
If the delay slot instruction has a second data transfer, two checks are performed in step 2, as in
the above case (Instructions that make two accesses to memory).
If the accepted exception (the highest-priority exception) is a delay slot instruction re-
execution type exception, the branch instruction PR register write operation (PC → PR
operation performed in a BSR, BSRF, or JSR instruction) is not disabled. Note that in this
case, the contents of PR register are not guaranteed.
levels 1 and 2 in the delayed branch instruction.
levels 1 and 2 in the delay slot instruction.
branch instruction.
instruction.
level 3 in the delay slot instruction. (There is no priority ranking between these two.)
level 4 in the delay slot instruction. (There is no priority ranking between these two.)