r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 1851

Manufacturer Part Number

r5s77631ay266bgv

Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series

Manufacturer

Renesas Electronics Corporation.

1. Table 41.4 shows the relation between the operand sizes specified using the match condition

Table 41.4 Relation between Operand Sizes and Address Bits to be Compared

2. When the data value is included in the channel 1 match conditions:

Selected Operand Size

Operand size is not included in the

match conditions

setting register (CBR0 or CBR1) and the address bits to be compared for the operand access

cycle break.

The above table means that if address H'00001003 is set in the match address setting register

(CAR0 or CAR1), for example, the match condition is satisfied for the following access cycles

(assuming that all the other conditions are satisfied):

 Longword access to address H'00001000

 Word access to address H'00001002

 Byte access to address H'00001003

If the data value is included in the match conditions, be sure to select the quadword, longword,

word, or byte as the operand size using the operand size select bit (SZ) of the match condition

setting register (CBR1), and also set the match data setting register (CDR1) and the match data

mask setting register (CDMR1). With these settings, the match condition is satisfied when

both of the address and data conditions are satisfied. The data value and mask control for byte

access, word access, and longword access should be set in bits 7 to 0, 15 to 0, and 31 to 0 in

the bits CDR1 and CDMR1, respectively. For quadword access, 64-bit data is divided into the

upper and lower 32-bit data units, and each unit is independently compared with the specified

condition. When either the upper or lower 32-bit data unit satisfies the match condition, the

match condition for the 64-bit data is determined to be satisfied.

Operand Access Cycle Break

Address Bits to be Compared

Address bits A31 to A3

Address bits A31 to A1

Address bits A31 to A0

Address bits A31 to A3 for quadword access

Address bits A31 to A2 for longword access

Address bits A31 to A1 for word access

Address bits A31 to A0 for byte access

Address bits A31 to A2

Rev. 1.00 Oct. 01, 2007 Page 1785 of 1956

Section 41 User Break Controller (UBC)

REJ09B0256-0100