r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 1044
r5s77631ay266bgv
Manufacturer Part Number
r5s77631ay266bgv
Description
Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.R5S77631AY266BGV.pdf
(2026 pages)
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Section 23 Gigabit Ethernet Controller (GETHER)
23.4.9
The GETHER should be activated by the following procedure:
(1)
1. Perform a power-on reset.
2. Start the E-DMAC transmitter and receiver (activation of descriptor engine).
• Set ENT to 1 and ENR to 1 in EDSR.
3. Perform a software reset.
• Set SWRR to 1 and SWRT to 1 in EDMR simultaneously.
4. Initialize the descriptor entry table.
5. Confirm cancellation of the software reset.
• Check that the SWRR and SWRT bits in EDMR are cleared to 0.
(2)
The address of a descriptor ring configured in memory is registered in the descriptor entry table.
1. Transmit Descriptor Setting
• Set TDLAR.
• Set TDFAR.
• Set TDFXR.
• Set TDFFR. When the descriptor indicated by TDFXR is the last descriptor in the descriptor
Rev. 1.00 Oct. 01, 2007 Page 978 of 1956
REJ09B0256-0100
Interrupt
Interrupt with
transfer
between port
0 and port 1
(GEINT2)
list, set H'00000001.
Reset
Registration of Descriptor Ring
Activation Procedure
Interrupt Source
E-MAC-1 Too-Long Frame Receive
E-MAC-1 Too-Short Frame Receive
E-MAC-1 Frame Receive Error
E-MAC-1 CRC Error Frame Receive
Register and Bit
TSU_FWSR.RINT41 When the interrupt
TSU_FWSR.RINT31 When the interrupt
TSU_FWSR.RINT21 When the interrupt
TSU_FWSR.RINT11 When the interrupt
Interrupt Generated
Timing
source is detected
source is detected
source is detected
source is detected
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