r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 11

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

6.6
6.7
6.8
Section 7 Caches ................................................................................................187
7.1
7.2
7.3
7.4
7.5
7.6
6.5.4
6.5.5
6.5.6
6.5.7
Memory-Mapped TLB Configuration................................................................................ 172
6.6.1
6.6.2
6.6.3
6.6.4
32-Bit Address Extended Mode ......................................................................................... 177
6.7.1
6.7.2
6.7.3
6.7.4
6.7.5
6.7.6
Usage Notes ....................................................................................................................... 186
Features.............................................................................................................................. 187
Register Descriptions ......................................................................................................... 190
7.2.1
7.2.2
7.2.3
7.2.4
Operand Cache Operation.................................................................................................. 197
7.3.1
7.3.2
7.3.3
7.3.4
7.3.5
7.3.6
Instruction Cache Operation .............................................................................................. 202
7.4.1
7.4.2
7.4.3
Cache Operation Instruction .............................................................................................. 204
7.5.1
7.5.2
Memory-Mapped Cache Configuration ............................................................................. 206
Data TLB Multiple Hit Exception ........................................................................ 169
Data TLB Miss Exception .................................................................................... 169
Data TLB Protection Violation Exception............................................................ 170
Initial Page Write Exception................................................................................. 171
ITLB Address Array ............................................................................................. 173
ITLB Data Array................................................................................................... 174
UTLB Address Array............................................................................................ 175
UTLB Data Array ................................................................................................. 176
Overview of 32-Bit Address Extended Mode....................................................... 178
Transition to 32-Bit Address Extended Mode ...................................................... 178
Privileged Space Mapping Buffer (PMB) Configuration ..................................... 179
PMB Function....................................................................................................... 181
Memory-Mapped PMB Configuration.................................................................. 182
Notes on Using 32-Bit Address Extended Mode .................................................. 184
Cache Control Register (CCR) ............................................................................. 191
Queue Address Control Register 0 (QACR0)....................................................... 193
Queue Address Control Register 1 (QACR1)....................................................... 194
On-Chip Memory Control Register (RAMCR) .................................................... 195
Read Operation ..................................................................................................... 197
Prefetch Operation ................................................................................................ 198
Write Operation .................................................................................................... 199
Write-Back Buffer ................................................................................................ 201
Write-Through Buffer........................................................................................... 201
OC Two-Way Mode ............................................................................................. 201
Read Operation ..................................................................................................... 202
Prefetch Operation ................................................................................................ 203
IC Two-Way Mode............................................................................................... 203
Coherency between Cache and External Memory ................................................ 204
Prefetch Operation ................................................................................................ 205
Rev. 1.00 Oct. 01, 2007 Page xi of lxvi