r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 408

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r5s77631ay266bgv

Manufacturer Part Number
r5s77631ay266bgv
Description
Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
Manufacturer
Renesas Electronics Corporation.
Datasheet
Section 11 Local Bus State Controller (LBSC)
Rev. 1.00 Oct. 01, 2007 Page 342 of 1956
REJ09B0256-0100
Bit
23
22 to 20 IWRWS
19
18 to 16 IWRRD
Bit Name
Initial
Value
0
111
0
111
R/W
R
R
R/W
R/W
Description
Reserved
This bit is always read as 0. The write value should
always be 0.
Idle Cycles between Read-Write to Same Space
Specify the number of idle cycles to be inserted after an
access to a memory connected to the space is
completed. The target cycles are read-write cycles to
the same space. For details, see section 11.5.8, Wait
Cycles between Accesses.
000: No idle cycle inserted
001: 1 idle cycle inserted
010: 2 idle cycles inserted
011: 3 idle cycles inserted
100: 4 idle cycles inserted
101: 5 idle cycles inserted
110: 6 idle cycles inserted
111: 7 idle cycles inserted
Reserved
This bit is always read as 0. The write value should
always be 0.
Idle Cycles between Read-Read to Different Spaces
Specify the number of idle cycles to be inserted after an
access to a memory connected to the space is
completed. The target cycles are read-read cycles to
different spaces. For details, see section 11.5.8, Wait
Cycles between Accesses.
000: No idle cycle inserted
001: 1 idle cycle inserted
010: 2 idle cycles inserted
011: 3 idle cycles inserted
100: 4 idle cycles inserted
101: 5 idle cycles inserted
110: 6 idle cycles inserted
111: 7 idle cycles inserted

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