r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 36

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

Section 41 User Break Controller (UBC)........................................................ 1759
41.1 Features............................................................................................................................ 1759
41.2 Register Descriptions....................................................................................................... 1761
41.3 Operation Description...................................................................................................... 1781
41.4 User Break Debugging Support Function ........................................................................ 1789
41.5 User Break Examples....................................................................................................... 1791
41.6 Usage Notes ..................................................................................................................... 1795
Section 42 User Debugging Interface (H-UDI)............................................... 1797
42.1 Features............................................................................................................................ 1797
42.2 Input/Output Pins............................................................................................................. 1799
42.3 Boundary Scan TAP Controllers (IDCODE, EXTEST, SAMPLE/PRELOAD, and
42.4 Register Descriptions....................................................................................................... 1802
42.5 Operation ......................................................................................................................... 1823
42.6 Usage Notes ..................................................................................................................... 1824
Rev. 1.00 Oct. 01, 2007 Page xxxvi of lxvi
41.2.1 Match Condition Setting Registers 0 and 1 (CBR0 and CBR1) ......................... 1763
41.2.2 Match Operation Setting Registers 0 and 1 (CRR0 and CRR1) ......................... 1770
41.2.3 Match Address Setting Registers 0 and 1 (CAR0 and CAR1)............................ 1772
41.2.4 Match Address Mask Setting Registers 0 and 1 (CAMR0 and CAMR1)........... 1774
41.2.5 Match Data Setting Register 1 (CDR1) .............................................................. 1776
41.2.6 Match Data Mask Setting Register 1 (CDMR1) ................................................. 1777
41.2.7 Execution Count Break Register 1 (CETR1)...................................................... 1778
41.2.8 Channel Match Flag Register (CCMFR) ............................................................ 1779
41.2.9 Break Control Register (CBCR) ......................................................................... 1780
41.3.1 Definition of Words Related to Accesses ........................................................... 1781
41.3.2 User Break Operation Sequence ......................................................................... 1782
41.3.3 Instruction Fetch Cycle Break ............................................................................ 1784
41.3.4 Operand Access Cycle Break ............................................................................. 1785
41.3.5 Sequential Break................................................................................................. 1787
41.3.6 Program Counter Value to be Saved................................................................... 1788
BYPASS)......................................................................................................................... 1800
42.4.1 Instruction Register (SDIR) ................................................................................ 1803
42.4.2 Interrupt Source Register (SDINT)..................................................................... 1804
42.4.3 Bypass Register (SDBPR) .................................................................................. 1805
42.4.4 Boundary Scan Register (SDBSR) ..................................................................... 1805
42.5.1 TAP Control ....................................................................................................... 1823
42.5.2 H-UDI Reset ....................................................................................................... 1824
42.5.3 H-UDI Interrupt .................................................................................................. 1824