r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 406

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

Section 11 Local Bus State Controller (LBSC)
11.4.3
CSnBCR is a 32-bit readable/writable register that specifies the bus width for area n (n = 0 to 2
and 4 to 6), numbers of wait, setup, and hold cycles to be inserted, burst length, and memory
types.
Some types of memory continue to drive the data bus immediately after the read signal is
inactivated. Therefore, a data bus collision may occur when there is consecutive memory access to
different areas or writing to a memory immediately after reading. This LSI automatically inserts
the number of idle cycles set by CSnBCR to prevent data bus collision. During idle cycles,
corresponding signals CS0 to CS2, CS4, CS5/CE1A, CS6/CE1B, RD, WE, CE2A, CE2B, and BS
are not asserted and RDWR is in the high state and the data is not driven.
CSnBCR is initialized to H'7777 7770 by a power-on reset or a manual reset.
Initial value:
Initial value:
Rev. 1.00 Oct. 01, 2007 Page 340 of 1956
REJ09B0256-0100
R/W:
R/W:
Bit:
Bit:
CSn Bus Control Register (CSnBCR)
31
15
R
R
0
0
R/W
R/W
30
14
1
1
IWRRS
IWW
R/W
R/W
29
13
1
1
R/W
R/W
28
12
1
1
R/W
27
11
R
0
0
BST
R/W
R/W
26
10
1
1
IWRWD
R/W*
R/W
25
1
9
1
SZ
R/W*
R/W
24
1
8
1
RDSPL
R/W
23
R
0
7
0
R/W
R/W
22
1
6
1
IWRWS
R/W
R/W
BW
21
1
5
1
R/W
R/W
20
1
4
1
R/W*
MPX
19
R
0
3
0
R/W
R/W
18
1
2
0
IWRRD
TYPE
R/W
R/W
17
1
1
0
R/W
R/W
16
1
0
0