r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 1198

Manufacturer Part Number

r5s77631ay266bgv

Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series

Manufacturer

Renesas Electronics Corporation.

Section 28 Serial Communication Interface with FIFO/IrDA Interface (SCIF/IrDA)

Rev. 1.00 Oct. 01, 2007 Page 1132 of 1956

REJ09B0256-0100

Receive Interrupt Enable

Enables or disables generation of a receive-data-full

interrupt (RXI) request when the RDF flag or DR flag in

SCFSR is set to 1, a receive-error interrupt (ERI)

request when the ER flag in SCFSR is set to 1, and a

break interrupt (BRI) request when the BRK flag in

SCFSR or the ORER flag in SCLSR is set to 1.

0: Receive-data-full interrupt (RXI) request, receive-

1: Receive-data-full interrupt (RXI) request, receive-

Note: An RXI interrupt request can be cleared by

Transmit Enable

Enables or disables the start of serial transmission by

Serial transmission is started when transmit data is

written to SCFTDR while the TE bit is set to 1.

0: Transmission disabled

1: Transmission enabled*

Note: SCSMR and SCFCR settings must be made, the

error interrupt (ERI) request, and break interrupt

(BRI) request disabled

error interrupt (ERI) request, and break interrupt

(BRI) request enabled

reading 1 from the RDF or DR flag, then clearing

the flag to 0, or by clearing the RIE bit to 0. ERI

and BRI interrupt requests can be cleared by

reading 1 from the ER, BRK, or ORER flag, then

clearing the flag to 0, or by clearing the RIE and

REIE bits to 0.

transmission format decided, and the transmit

FIFO reset, before the TE bit is set to 1.