r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 1070

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

Section 25 Stream Interface (STIF)
Rev. 1.00 Oct. 01, 2007 Page 1004 of 1956
REJ09B0256-0100
Bit
15
14
13, 12
11 to 9
8
Bit Name
CKSL

CKDV[1:0] 00

REQEN
Initial
Value
0
0
All 0
0
R/W
R/W
R
R/W
R
R/W
Description
Operating Clock
Selects the source clock for the stream data transfer
clock
0: Peripheral clock 0 is used as the stream data
1: External input clock is used as the stream data
Reserved
This bit is always read as 0. The write value should
always be 0.
Operating Clock Division Ratio
These bits specify the division ratio when peripheral
clock 0 is selected as the stream data transfer clock.
00: Stream data transfer clock is 1/2 of peripheral
01: Stream data transfer clock is 1/4 of peripheral
10: Stream data transfer clock is 1/8 of peripheral
11: Setting prohibited
Reserved
These bits are always read as 0. The write value
should always be 0.
ST_REQ Pin Enable
Selects whether or not to use the ST_REQ pin.
0: ST_REQ pin is not used
1: ST_REQ pin is used
(1) At reception: ST_REQ is output when the free
(2) At transmission: Transmission is stopped when
transfer clock (stream data transfer clock is output
from the ST_CLK pin)
transfer clock (stream data transfer clock is input
from the ST_CLK pin)
space in FIFO is 8 bytes or less
ST_REQ is input
clock 0
clock 0
clock 0